KR920018895A - 트랜지스터의 공통소오스 콘택구조 - Google Patents

트랜지스터의 공통소오스 콘택구조 Download PDF

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KR920018895A
KR920018895A KR1019910003646A KR910003646A KR920018895A KR 920018895 A KR920018895 A KR 920018895A KR 1019910003646 A KR1019910003646 A KR 1019910003646A KR 910003646 A KR910003646 A KR 910003646A KR 920018895 A KR920018895 A KR 920018895A
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South Korea
Prior art keywords
common source
diffusion region
contact
contact structure
substrate
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KR1019910003646A
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English (en)
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KR940001814B1 (ko
Inventor
안병진
김종오
송복남
이영춘
Original Assignee
정몽헌
현대전자산업 주식회사
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Priority to KR1019910003646A priority Critical patent/KR940001814B1/ko
Publication of KR920018895A publication Critical patent/KR920018895A/ko
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Publication of KR940001814B1 publication Critical patent/KR940001814B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

트랜지스터의 공통소오스 콘택구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1B도는 제1도의 B-B′를 따라 절단한 반도체 소자의 단면도.
제2도는 제1B도의 구조에서 본 발명에 의해 기판 콘택용 확산영역이 형성되고 소오스와 도전층에 의해 접속된 구조를 도시한 단면도.

Claims (4)

  1. 고집적 반도체 소자의 트랜지스터 셀이 배열되고 실리콘기판 외주면에는 기판접지용 확산영역이 형성되고 다수개의 셀을 한단위로 설정하여 공통소오스에 금속층을 콘택시켜서 접지시키는 반도체 소자에 있어서, 소자동 작시 내부의 트랜지스터에서 발생된 기생 기판전류를 효과적으로 접지시키기 위하여, 액티브영역을 따라 형성되는 공통소오스 확산영역의 중에서 금속층이 콘택되는 예정된 공통소오스 확산영역에 실리콘 기판과 동일타입의 기판콘택용 확산영역을 형성하고, 상기 공통소오스용 확산영역과 기판콘택용 확산영역 상부에 도전층을 형성하여 상호 접속되도록 한다음, 이 도전층에 공통소오스를 접지시키는 금속층을 콘택시킨 것을 특징으로 하는 트랜지스터의 공통소오스 콘택구조.
  2. 제1항에 있어서, 상기 공통소오스용 확산영역과 기판콘택용 확산영역 상부에 형성되는 도전층은 금속실리사이드인 것을 특징으로 하는 트랜지스터의 공통소오스 콘택구조, 공통소오스 콘택구조.
  3. 제1항에 있어서, 상기 공통소오스용 확산영역이 P+형일때 접지콘택용 확산영역은 n+형인 것을 특징으로 하는 트랜지스터의 공통소오스 콘택구조.
  4. 제1항에 있어서, 상기 공통소오스용 확산영역이 n+형일 때 접지콘택용 확산영역은 P+형인 것을 특징으로 하는 트랜지스터의 공통소오스 콘택구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019910003646A 1991-03-07 1991-03-07 트랜지스터의 공통소오스 콘택구조 KR940001814B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910003646A KR940001814B1 (ko) 1991-03-07 1991-03-07 트랜지스터의 공통소오스 콘택구조

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910003646A KR940001814B1 (ko) 1991-03-07 1991-03-07 트랜지스터의 공통소오스 콘택구조

Publications (2)

Publication Number Publication Date
KR920018895A true KR920018895A (ko) 1992-10-22
KR940001814B1 KR940001814B1 (ko) 1994-03-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910003646A KR940001814B1 (ko) 1991-03-07 1991-03-07 트랜지스터의 공통소오스 콘택구조

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KR (1) KR940001814B1 (ko)

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KR940001814B1 (ko) 1994-03-09

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