KR920015623A - 반도체 소자 및 그 제조방법 - Google Patents
반도체 소자 및 그 제조방법 Download PDFInfo
- Publication number
- KR920015623A KR920015623A KR1019920000667A KR920000667A KR920015623A KR 920015623 A KR920015623 A KR 920015623A KR 1019920000667 A KR1019920000667 A KR 1019920000667A KR 920000667 A KR920000667 A KR 920000667A KR 920015623 A KR920015623 A KR 920015623A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- insulating layer
- conductive
- region
- etch stopper
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims 9
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 5
- 239000004020 conductor Substances 0.000 claims 3
- 238000000034 method Methods 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14806—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
- H01L27/1485—Frame transfer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66946—Charge transfer devices
- H01L29/66954—Charge transfer devices with an insulated gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 래스터 전사형의 전하 결합 화상 센서에 대한 선도, 제2도는 본 발명에 따른 클록 라인 및 클록 전극간에 도해적으로 표시된 접속과 제1도에 그려진 소자의 부분 도시도, 제3도는 제2도에 따른 장치의 일부분에 대한 단면도.
Claims (6)
- 한 표면에서 적어도 2개의 전도 영역을 지닌 하나 또는 몇개의 회로 요소를 가진 반도체 본체를 포함하며, 그 표면이 절연 층 내의 접촉 윈도우에 의하여 전도 영역과 상호 접속하고 적어도 실제적으로 그 자체의 전체 두께 이상으로 절연 층 속으로 오목 들어간 전도체 트랙이 제공되는 절연층으로 코팅된 반도체 소자에 있어서, 에칭 스토퍼 층은 전도 영역 사이의 삽입된 영역에 제공하고, 상기 층은 절연층의 아래 부분과 전도체 트랙을 분리시키고 절연 층에 관하여 선택적으로 에칭 할 수 있는 물질을 포함하며, 에칭 스토퍼 층이 공통 층으로부터 제조된 일부분의 층 패턴을 형성하는 동안, 상기 패턴은 소자내의 어떤 다른 곳에 또한 부분을 에칭 스토퍼 층 가까이에 포함하는 것을 특징으로 하는 반도체소자.
- 제1항에 있어서, 상기 에칭 스토퍼 층은 금속 또는 반도체 물질, 특히 다결정 실리콘을 포함하는 것을 특징으로 하는 반도체 소자.
- 선행항 중 어느 한 항에 있어서, 상기 2개의 전도 영역은 서로 나란히 놓여진 게이트 전극의 범위로 하여, 전하 결합 소자의 게이트 전극을 형성하고 공통 배선 층의 일부를 형성하는 것을 특징으로 하는 반도체 소자.
- 제3항에 있어서, 상기 게이트 전극은 다결정 실리콘의 제1층으로부터 제조되는 것과, 에칭 스토퍼 층은 절연층의 삽입된 부분에 의해 제1층과 전기적으로 분리된 제2다결정 실리콘 층으로부터 제조되며, 제2다결정 실리콘 층의 두께는 제1다결정 실리콘 층의 것보다 두껍게 하는 것을 특징으로 하는 반도체 소자.
- 한 표면에서 적어도 2개의 전도 영역을 지닌 하나 또는 몇개의 회로 요소를 가진 반도체 본체를 포함하며, 그 표면이 절연 층 내의 접촉 윈도우에 의하여 전도 영역과 상호 접속하고 적어도 실제적으로 그 자체의 전체 두께이상으로 절연 층속으로 오목 들어간 전도체 트랙이 형성되는 절연층으로 코팅된 반도체 소자를 제조하는 방법에 있어서, 전도 영역이 제공되어 진 후, 절연 층은 그 자체의 두께의 제1부분 위에 형성되며, 절연 층에 관하여 선택적으로 에칭할 수 있는 전도 물질의 에칭 스토퍼 층은 전도 영역 사이에 놓여진 중간 영역내의 상기 부분상에 형성되며, 그 뒤에 절연 층은 그 자체의 두께의 제2부분상에 제공되며, 그리고 그 절연 층은 형성될 전도 트랙의 영역에서 에칭 처리되어지며, 그동안 상기 중간 영역에서 에칭 스토퍼 층에 이르기 까지와 접촉 윈도우의 영역에서 전도 영역에 이르기 까지 제거되며, 그리고 그와 같은 형태가 얻어진 후 전도 층으로 덮여지며, 그로부터 오목 들어간 전도 트랙은 다시 에칭함으로써 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제5항에 있어서, 접촉 윈도우의 중간 영역 및 영역에서 절연 층을 제거하기 위한 에칭 처리는 이방성적으로 수행되는 것을 특징으로 하는 반도체 소자의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL9100094A NL9100094A (nl) | 1991-01-21 | 1991-01-21 | Halfgeleiderinrichting en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting. |
NL9100094 | 1991-01-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920015623A true KR920015623A (ko) | 1992-08-27 |
KR100273070B1 KR100273070B1 (ko) | 2000-12-01 |
Family
ID=19858750
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920000667A KR100273070B1 (ko) | 1991-01-21 | 1992-01-18 | 반도체 소자 및 그 제조방법 |
Country Status (6)
Country | Link |
---|---|
US (2) | US5396092A (ko) |
EP (1) | EP0496443B1 (ko) |
JP (1) | JP3048459B2 (ko) |
KR (1) | KR100273070B1 (ko) |
DE (1) | DE69226887T2 (ko) |
NL (1) | NL9100094A (ko) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL9100094A (nl) * | 1991-01-21 | 1992-08-17 | Koninkl Philips Electronics Nv | Halfgeleiderinrichting en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting. |
DE69428394T2 (de) * | 1993-05-21 | 2002-07-04 | Koninkl Philips Electronics Nv | Ladungsgekoppelte Bildaufnahmeanordnung |
EP0625800B1 (en) * | 1993-05-21 | 2001-09-26 | Koninklijke Philips Electronics N.V. | Charge coupled imaging device |
US5382545A (en) * | 1993-11-29 | 1995-01-17 | United Microelectronics Corporation | Interconnection process with self-aligned via plug |
US5635421A (en) * | 1995-06-15 | 1997-06-03 | Taiwan Semiconductor Manufacturing Company | Method of making a precision capacitor array |
US5719075A (en) * | 1995-07-31 | 1998-02-17 | Eastman Kodak Company | Method of making a planar charge coupled device with edge aligned implants and electrodes connected with overlying metal |
JPH09153545A (ja) * | 1995-09-29 | 1997-06-10 | Toshiba Corp | 半導体装置及びその製造方法 |
US6008121A (en) * | 1996-03-19 | 1999-12-28 | Siemens Aktiengesellschaft | Etching high aspect contact holes in solid state devices |
JPH09270461A (ja) * | 1996-03-29 | 1997-10-14 | Mitsubishi Electric Corp | 半導体装置 |
US5652173A (en) * | 1996-05-09 | 1997-07-29 | Philips Electronics North America Corporation | Monolithic microwave circuit with thick conductors |
EP0925604B1 (en) * | 1997-05-29 | 2008-07-09 | Nxp B.V. | A method of manufacturing an electronic device whereby a conductive layer is provided on an electrically insulating substrate, from which layer a conductor pattern is formed |
US5989784A (en) * | 1998-04-06 | 1999-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch recipe for embedded DRAM passivation with etch stopping layer scheme |
EP1374301A2 (en) * | 2001-03-21 | 2004-01-02 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device with metallization layers interconnected by tungsten plugs |
DE10320166B4 (de) * | 2002-05-16 | 2007-06-06 | Dalsa Corp., Waterloo | Pixelentwurf für CCD-Bildsensoren |
US6562711B1 (en) * | 2002-06-28 | 2003-05-13 | Intel Corporation | Method of reducing capacitance of interconnect |
US8166438B2 (en) * | 2009-01-28 | 2012-04-24 | Oracle America, Inc. | Low RC local clock distribution |
US8245781B2 (en) * | 2009-12-11 | 2012-08-21 | Schlumberger Technology Corporation | Formation fluid sampling |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4163239A (en) * | 1971-12-30 | 1979-07-31 | Texas Instruments Incorporated | Second level phase lines for CCD line imager |
US4291328A (en) * | 1979-06-15 | 1981-09-22 | Texas Instruments Incorporated | Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon |
US4488166A (en) * | 1980-12-09 | 1984-12-11 | Fairchild Camera & Instrument Corp. | Multilayer metal silicide interconnections for integrated circuits |
JPS5966165A (ja) * | 1982-10-08 | 1984-04-14 | Hitachi Ltd | 電極配線およびその製造方法 |
JPS601846A (ja) * | 1983-06-18 | 1985-01-08 | Toshiba Corp | 多層配線構造の半導体装置とその製造方法 |
NL8501339A (nl) * | 1985-05-10 | 1986-12-01 | Philips Nv | Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan. |
JPS61280638A (ja) * | 1985-06-06 | 1986-12-11 | Toshiba Corp | 半導体装置の製造方法 |
US4808552A (en) * | 1985-09-11 | 1989-02-28 | Texas Instruments Incorporated | Process for making vertically-oriented interconnections for VLSI devices |
US4789648A (en) * | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
ATE80750T1 (de) * | 1986-12-17 | 1992-10-15 | Advanced Micro Devices Inc | Aneinandergefuegte kontaktstruktur mit vermindertem flaechenbedarf. |
JPH02134992A (ja) * | 1988-11-15 | 1990-05-23 | Matsushita Electron Corp | 固体撮像素子 |
NL9100094A (nl) * | 1991-01-21 | 1992-08-17 | Koninkl Philips Electronics Nv | Halfgeleiderinrichting en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting. |
-
1991
- 1991-01-21 NL NL9100094A patent/NL9100094A/nl not_active Application Discontinuation
-
1992
- 1992-01-14 DE DE69226887T patent/DE69226887T2/de not_active Expired - Fee Related
- 1992-01-14 EP EP92200079A patent/EP0496443B1/en not_active Expired - Lifetime
- 1992-01-18 KR KR1019920000667A patent/KR100273070B1/ko not_active IP Right Cessation
- 1992-01-21 JP JP4008554A patent/JP3048459B2/ja not_active Expired - Fee Related
-
1994
- 1994-04-08 US US08/225,403 patent/US5396092A/en not_active Expired - Fee Related
- 1994-11-29 US US08/346,947 patent/US5536678A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69226887D1 (de) | 1998-10-15 |
NL9100094A (nl) | 1992-08-17 |
US5396092A (en) | 1995-03-07 |
US5536678A (en) | 1996-07-16 |
KR100273070B1 (ko) | 2000-12-01 |
JP3048459B2 (ja) | 2000-06-05 |
DE69226887T2 (de) | 1999-04-08 |
EP0496443B1 (en) | 1998-09-09 |
JPH04302472A (ja) | 1992-10-26 |
EP0496443A1 (en) | 1992-07-29 |
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