KR920013773A - S / D device manufacturing method using selective epitaxy - Google Patents

S / D device manufacturing method using selective epitaxy Download PDF

Info

Publication number
KR920013773A
KR920013773A KR1019900022472A KR900022472A KR920013773A KR 920013773 A KR920013773 A KR 920013773A KR 1019900022472 A KR1019900022472 A KR 1019900022472A KR 900022472 A KR900022472 A KR 900022472A KR 920013773 A KR920013773 A KR 920013773A
Authority
KR
South Korea
Prior art keywords
selective epitaxy
device manufacturing
epitaxy
regions
oxide film
Prior art date
Application number
KR1019900022472A
Other languages
Korean (ko)
Other versions
KR940004263B1 (en
Inventor
신형선
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900022472A priority Critical patent/KR940004263B1/en
Publication of KR920013773A publication Critical patent/KR920013773A/en
Application granted granted Critical
Publication of KR940004263B1 publication Critical patent/KR940004263B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음No content

Description

선택 에피택시를 이용한 S/D소자 제조방법S / D device manufacturing method using selective epitaxy

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 S/D소자 제조 공정도2 is a process chart of manufacturing S / D device according to the present invention

Claims (1)

게이트 옥사이드(Gate Oxide)다결정 실리콘 산화막으로 구성된 게이트를 패터닝(Patterning)하고, 10-18-3정도의 n영역을 임플랜드(Implant)로 형성하고, 산화막을 이용하여 싸이드웰(Side Wall)을 형성하고,RTP를 이용한 선택에피택시로10-16-3정도의 n-영역을 배어실리콘(Bare Silicon)이 오픈된 S/D부분에만 형성하고, 산화막을 이용하여 싸이드웰을 형성한 다음에 10-20-3정도의 n+영역을 임플랜테이션(Zmplantation)하여 형성하고 n영역과 만나도록하여 구성된 것을 특징으로 하는 선택 에피텍시를 이용한 S/D소자 제조방법.Gate oxide Patterned gates made of polycrystalline silicon oxide film, n-regions of about 10 -18 cm -3 are formed with implants, and sidewalls are formed using oxide films. After forming n-regions of about 10 -16 cm -3 by selective epitaxy using RTP, only the S / D portions in which bare silicon is opened are formed, and a side well is formed using an oxide film. 10 -20-3 degrees of the n + implantation zone (Zmplantation) to form and process for producing S / D device using the selected epitaxy, characterized in that is configured so as to meet with the region n. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900022472A 1990-12-29 1990-12-29 Manufacturing method of semiconductor using selective epitexy KR940004263B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900022472A KR940004263B1 (en) 1990-12-29 1990-12-29 Manufacturing method of semiconductor using selective epitexy

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900022472A KR940004263B1 (en) 1990-12-29 1990-12-29 Manufacturing method of semiconductor using selective epitexy

Publications (2)

Publication Number Publication Date
KR920013773A true KR920013773A (en) 1992-07-29
KR940004263B1 KR940004263B1 (en) 1994-05-19

Family

ID=19308974

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900022472A KR940004263B1 (en) 1990-12-29 1990-12-29 Manufacturing method of semiconductor using selective epitexy

Country Status (1)

Country Link
KR (1) KR940004263B1 (en)

Also Published As

Publication number Publication date
KR940004263B1 (en) 1994-05-19

Similar Documents

Publication Publication Date Title
KR920013773A (en) S / D device manufacturing method using selective epitaxy
JPS5395582A (en) Manufacture for semiconductor device
GB2022922A (en) A field-effect transistor forming a memory point and a process for its production
JPS5437584A (en) Field effect semiconductor device of insulation gate type
JPS52127181A (en) Insulated gate type filed effect transistor
JPS53144686A (en) Production of semiconductor device
KR920015433A (en) MOS transistor process method
KR920013775A (en) Trench using transistor manufacturing method
KR920007213A (en) Channel Implant Method Using Gate Polysilicon
JPS5317284A (en) Production of semiconductor device
KR920015611A (en) CMOS manufacturing method
KR920015592A (en) LDD structure transistor manufacturing method
KR920017215A (en) SOI manufacturing method using silicon growth
JPS52144980A (en) Sos semiconductor device
JPS53139985A (en) Production of mis type transistors
JPS5283067A (en) Production of mis type semiconductor device
KR910020798A (en) CMOS transistor manufacturing method
JPS5389376A (en) Production of semiconductor device
KR920007165A (en) CMOS device manufacturing method
KR920013746A (en) LDD structure transistor manufacturing method
KR930009136A (en) Solid-state imaging device
JPS52136584A (en) Production of insulated gate type field effect transistors
KR910017671A (en) Sideol spacer manufacturing method
KR910017672A (en) MOSFET manufacturing method
KR940016590A (en) Oxide film formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
AMND Amendment
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

G160 Decision to publish patent application
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050422

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee