GB2022922A - A field-effect transistor forming a memory point and a process for its production - Google Patents
A field-effect transistor forming a memory point and a process for its productionInfo
- Publication number
- GB2022922A GB2022922A GB7920008A GB7920008A GB2022922A GB 2022922 A GB2022922 A GB 2022922A GB 7920008 A GB7920008 A GB 7920008A GB 7920008 A GB7920008 A GB 7920008A GB 2022922 A GB2022922 A GB 2022922A
- Authority
- GB
- United Kingdom
- Prior art keywords
- production
- field
- effect transistor
- transistor forming
- memory point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
An IGFET, having a floating gate 29 and a control 23, has a highly doped p (or n) region 20 aligned with the edges of the p (or n) channel region between source region 21 and drain region 22. <IMAGE>
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7817279A FR2428327A1 (en) | 1978-06-09 | 1978-06-09 | FIELD EFFECT TRANSISTOR CONSTITUTING A MEMORY POINT AND ITS MANUFACTURING METHOD |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2022922A true GB2022922A (en) | 1979-12-19 |
GB2022922B GB2022922B (en) | 1982-08-04 |
Family
ID=9209295
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB7920008A Expired GB2022922B (en) | 1978-06-09 | 1979-06-08 | Field-effect pransistor forming a memory point and a process for its production |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS54162977A (en) |
CA (1) | CA1147465A (en) |
DE (1) | DE2923365A1 (en) |
FR (1) | FR2428327A1 (en) |
GB (1) | GB2022922B (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1003222A1 (en) * | 1998-11-19 | 2000-05-24 | STMicroelectronics S.r.l. | Improved field-effect transistor and corresponding manufacturing method |
WO2000038245A1 (en) * | 1998-12-21 | 2000-06-29 | Lattice Semiconductor Corporation | Dual pocket, two sided program/erase non-volatile memory cell |
US6214666B1 (en) | 1998-12-18 | 2001-04-10 | Vantis Corporation | Method of forming a non-volatile memory device |
US6215700B1 (en) | 1999-01-07 | 2001-04-10 | Vantis Corporation | PMOS avalanche programmed floating gate memory cell structure |
US6232631B1 (en) | 1998-12-21 | 2001-05-15 | Vantis Corporation | Floating gate memory cell structure with programming mechanism outside the read path |
US6294809B1 (en) | 1998-12-28 | 2001-09-25 | Vantis Corporation | Avalanche programmed floating gate memory cell structure with program element in polysilicon |
US6326663B1 (en) | 1999-03-26 | 2001-12-04 | Vantis Corporation | Avalanche injection EEPROM memory cell with P-type control gate |
US6424000B1 (en) | 1999-05-11 | 2002-07-23 | Vantis Corporation | Floating gate memory apparatus and method for selected programming thereof |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1390135A (en) * | 1971-05-08 | 1975-04-09 | Matsushita Electric Ind Co Ltd | Insulated gate semiconductor device |
-
1978
- 1978-06-09 FR FR7817279A patent/FR2428327A1/en active Granted
-
1979
- 1979-06-08 GB GB7920008A patent/GB2022922B/en not_active Expired
- 1979-06-08 JP JP7214579A patent/JPS54162977A/en active Pending
- 1979-06-08 DE DE19792923365 patent/DE2923365A1/en not_active Withdrawn
- 1979-06-08 CA CA000329375A patent/CA1147465A/en not_active Expired
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1003222A1 (en) * | 1998-11-19 | 2000-05-24 | STMicroelectronics S.r.l. | Improved field-effect transistor and corresponding manufacturing method |
US6387763B1 (en) | 1998-11-19 | 2002-05-14 | Stmicroelectronics S.R.L. | Field-effect transistor and corresponding manufacturing method |
US6737715B2 (en) | 1998-11-19 | 2004-05-18 | Stmicroelectronics S.R.L. | Field-effect transistor and corresponding manufacturing method |
US6214666B1 (en) | 1998-12-18 | 2001-04-10 | Vantis Corporation | Method of forming a non-volatile memory device |
WO2000038245A1 (en) * | 1998-12-21 | 2000-06-29 | Lattice Semiconductor Corporation | Dual pocket, two sided program/erase non-volatile memory cell |
US6232631B1 (en) | 1998-12-21 | 2001-05-15 | Vantis Corporation | Floating gate memory cell structure with programming mechanism outside the read path |
US6282123B1 (en) | 1998-12-21 | 2001-08-28 | Lattice Semiconductor Corporation | Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell |
US6294809B1 (en) | 1998-12-28 | 2001-09-25 | Vantis Corporation | Avalanche programmed floating gate memory cell structure with program element in polysilicon |
US6215700B1 (en) | 1999-01-07 | 2001-04-10 | Vantis Corporation | PMOS avalanche programmed floating gate memory cell structure |
US6326663B1 (en) | 1999-03-26 | 2001-12-04 | Vantis Corporation | Avalanche injection EEPROM memory cell with P-type control gate |
US6424000B1 (en) | 1999-05-11 | 2002-07-23 | Vantis Corporation | Floating gate memory apparatus and method for selected programming thereof |
Also Published As
Publication number | Publication date |
---|---|
FR2428327A1 (en) | 1980-01-04 |
FR2428327B1 (en) | 1982-04-23 |
DE2923365A1 (en) | 1979-12-20 |
JPS54162977A (en) | 1979-12-25 |
CA1147465A (en) | 1983-05-31 |
GB2022922B (en) | 1982-08-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PE20 | Patent expired after termination of 20 years |
Effective date: 19990607 |