CA1147465A

CA1147465A - Floating gate injection field-effect transistor

Info

Publication number: CA1147465A
Application number: CA000329375A
Authority: CA
Inventors: Eugene Tonnel
Original assignee: Thomson CSF SA
Current assignee: Thales SA
Priority date: 1978-06-09
Filing date: 1979-06-08
Publication date: 1983-05-31
Also published as: JPS54162977A; FR2428327A1; GB2022922A; FR2428327B1; GB2022922B; DE2923365A1

Abstract

ABSTRACT OF THE DISCLOSURE

This invention relates to field-effect tran-sistors comprising a floating gate. The threshold voltage of a transistor such as this may be modified by the injection of electrical charge carriers at an inter-mediate level between the control gate and the substrate which is formed by the floating gate. The structure of the transistor is such that these injections of carriers are punctiform because the production process, which is automatically aligned, allows precise positioning of the overdoped injection regions. Application to electri-cally erased non-volatile memory circuits.

Description

~ 3L47~6~i 1 This invention relates to active electronic devices made of semiconductors and know~l as "non-volatile" memories.
In devices such as these, the information stored in the form of charges grouped in preferential regions of the device persists in the absence of electrical feeding of the circuit. Accordingly, the "writtenl' information, i.e. the information recorded in the memory, is maintained and kept ~
intact, even iE the hardware of which the memory forms part ~ - ;
is taken out of and then put back into operation.
Non-volatile memories comprise a plurality of elementary cells each forming a memory point which, depending on its state, corresponds to an upper or lower state of the Boolean logic. Each memory point comprises an active element of which the characterist~ics may~be modified in ; 15 dependence upon the information which~it is desired to ~- ~ memorise.
However~ there are several types~of so-called "non~
volatile" memories, depending on whet~.er their content is . . .
fixed at the production stage or variable according to the ~ 0 requirements oE the user. Memories of the first type include ; ~ the so-called l'read-only" memory~(ROM)~, of which the content ~ 1 is determined before their production and remains fixed because it is associated with the state of the memory on completion of production.
This lack of flexibility in the use of read-only memories was the beginning of memories which could be programmed by the user, these memories being known as programmable read-only memories (or PROM in short~. In programmable read-only memories, the content of the memory is recorded by processes such as the junction breakdown of a transistor or the blowout of a fuse in a circuit.
Although the programming of a memory by its user represents a significant advance, it is nevertheless attended by a serious disadvantage concerning the erasing function: unless the programme is reversible and unless an error can be erased or the content of a memory changed, it is necessary in such a case to~change the entire memory circuit. A solution based on another programming process provides for erasing by exposure to int~se ultraviolet ;~ ~
20 radiation. However, ~it is generally necessary in this ~ ;
process to stop the machine and to remove from it the - printed circuits comprising the memory circuits to expose them to the ultraviolet radi~tion, which represents another disadvantage.

; ; 3 ~ ~4~

1 The solution which combines the greatest number of advantages is undoubtedly that which uses electrical rneans for each of the three operations of writing, reading and era~ng the content of a memory. These electrically erased non-volatile memories are commonly known as erasable access read-only memories (EAROM in short). Because the time taken to write or erase an item of information is generally longer than the reading time, these memoriesare also known asread mostly memories (or RMM in short).
In electrically recordable and erasable non-volatile memories, which in the interests of simplicity will herein-after be referred to in short as EAROM's, it is possible to envisage memory points formed by a bipolar transistor.
In fact, the active element generally used is an insulated-gate field-effect transistor because the information keeps better with a transistor of this type.
One essential characteristic of these transistors is defined by the minimum "threshold" voltage which ~ s to be applied to the gate to make the device conductive. It is this threshold voltage which is modified to memorise an item of information, reading consisting in measuring the ~
voltage required to obtain conduction and to verify the ;;
state of the memory point.
There are thus three electrical states of the memory .

-1 according to the reading, writing or erasing operation.
If it is written that VDs is the voltage between the drain and source of the field-effect transistor and VG
the gate voltage, reading of the content of the memory is obtained by a voltage writing is obtained by means of a voltage and erasing by a voltage VDs G3 ~;~
substrate with in addition the inequations DS1C~ VDS2 ~ VDS
substrate and VG1 VG2 ~ VG3 to ensure that the reading voltage does not erase what has ;
been written.
According to the prior art, the threshold voltage of a field-effect transistor may be modified in two ways.
The first is to construct a transistor in which the insulation of the ga~te electrode is composed of two different dielectric layers: for example silicon oxide and nitride ~;~
in the case of MNOS (metaljnitride/oxide/silicon) transistors.
In this case, it is possible by applying a bipolar volta~ge~

~!
5 ~ ~
-, ~74~;

v 1 to the gate to charge or discharge the interface between the two dielectrics and hence to modify the threshold of the memory transistor. However, this solution is attended by two main difficulties:
- the memory point has to be insulated to enable polarity to be inverted for reading and erasing, - the improvement in the recording conditions results either in a reduction in retention or in a deterioration in the erasing of the memory point, characteristics which both depend on the control of a very thin oxide layer (20 to 50 Angstroms).
A second way of modifying the threshold voltage of a field-effect transistor is to charge a floating gate modified by injections of electrical charge carriers to which sufficient energy for overcoming the Si/SiO2 potent;al barrier has been imparted in the silicon. These so-called "hot" carriers are obtained in the subjacent junctions of the memory transistor biassed in the backward direction.
In this solution, the thicknesses of the gate di-electric may be conslderable because the carriers have acquired sufficient energy to reach the conduction band ~ `
of the dielectric. Accordingly, retention is very good, ~ ;
but the charge accumulated on the gate is difficult to el~minate.~

1~7~5 1 It is these elements, of the FAMOS (floating avalanche MOS) type, which were initially erased by exposing the dielectric to ultraviolet irradlation to make it conductive However, this prolonged operation results in complete erasing of the memory and in a module of special and complicated design.
There are other solutions which are more convenient than ultraviolet erasing and which enable the floating gate to be alternately charged ~nd discharged. Solutions such as these fall into two categories, depending on whether the charges injected into the gate during writing are re-emitted or compensated by charges of opposite type.
Solutions belonging to the first category, in which the stored chargeis are re-emitted or dissipated, require the use of high voltages or of a thin dielectric to enable the electrons stored on the floating gate to pass through the dielectric and to reach either the semiconductor substrate or another gate known as the control gate arranged above the floating gate.
~hen the flow of charges towards the substrate is confined to the thin oxide region o~ the source of the transistor for example, this region has to be doped before the floating gate is deposited and etched. However, thls :, eliminates the advantage~of automatic positioning which .. ~ .

~:

3~ 47~65 1 arises out of the inverse chronological order in the etching and diffusion operations which enables the positioning latitudes to be ignored and the size of the components to be reduced~
Where the charges are removed through the control gate, S it has been found by experiment that, in this case, erasing is much more effective when the floating grid is made of polycrystalline silicon of the P-type conductivity Although not strictly necessary, this condition does not readily lend itself to the construction of transistors having a faster N-conductivity channel and an N-gate.
In the so-called "silicon gate" technique, the drain, the source and the gate are generally doped simultaneously and therefore have the same type.
It thus appears that all the kno~n solutions for erasing the content of a re-recordable memory are attended by fundamental disadvantages either in regard to the operations involved in manufacturing the device or inregard to the user.
Ultraviolet erasing is long and delicate.
Solutions belonging to the second category, i.e.
solutions which enable the floating gate to be charged and discharged by charge compensation, are ~ot attended by these disadvantages. The floating gate is electrically charged and discharged by means of electrical particles injected~
from the sub-jacent layers which are the electron for the ~ 8 ~`
.,, ~,~.

~ ~7 ~ 5 1 negative charges and the "hole`' for the positive charges.
A hole corresponds to the absence of an electron and is therefore an imaginary particle having the same imaginary mass as the electron and the same electrical charge, but the opposite sign.
Thus, in the solutions based on charge compensation, the floating gate of the memory point transistor is negatively charged with hot electrons and then discharged, i~e. positively charged, with hot holes.
10The present invention relates to this type of non-volatile memory point in which the threshold voltage of the gate of the field-effect transistor is modified by compensation o~ the charges. The invention provides a new structure for this memory point transistor and also a process for its production.
More precisely, the present invention relates to a field-effect transistor forming an electrically recordable and erasable memory point and comprising, on the one hand, a source region and a drain region diffused into a substrate ~;
, of semiconductor material and, on the other hand, a control gate separated from the substrate by a dielectric layer in~
which a so-called floating insulated group is embedded, characterised in that a locally overdoped region9 which is automatically aligned with the lateral zones of the channel g ~: :

.

1 separating the source and the drain, ensures the puncti~orm localisation of the electrical charge carriers injected from the source and the drain towards the floating gate, thus modifying the threshold voltages of the transistor corresponding to the operations of reading, writing and erasing the content of the memory point.
The invention will be understood more easily Erom the following description in conjunction with the accompanying drawings, wherein:
Figure 1 is a diagram of the modification of a threshold voltage by dissipation of the charges.
Figure 2 is a diagram of the modification of a threshold voltage by compensation of the charges. ;
Figure 3 shows a prior art field-effect transistor in plan (a) and in section along two axes (b and c).
Figure 4 shows diagrams similar to Figure 3 of a field-effect transistor according to the invention.
Figure 5 illustrates the various stages (a to f) oE
the process for producing the memory point according to the invention.
Fig. 1 i$ a ~Elow diagram of the electrical charges in a field-effect transistor consisting of a source 1, a drain 2 and a control gate 3. The channel is the region which separates the source from the drain. The chQrges 6 in the ::

1 form of hot electrons injected from the drain 2 are stored at the interface between the two dielectric layers 4 and 5.
This interface is the equivalent of a floating gate. The threshold voltage of the control gate 3 is modified by the dissipation of the charges either towards the substrate in one itinerary, such as shown at 7, through a dielectric layer 4 or towards the control gate 3 in another itinerary, such as shown at 8, through the other dielectric layer 5O
Figure 2 diagrammatically illustrates the compensation of the charges. Fig. 2 shows the same con~ituent elements of a field-effect transistor, namely- the source 1, the drain 2 and the control gate 3. In contrast to the transistor shown in Fig. 1, however, the floating gate 9 is materialised by a semiconducting region which is preferably formed by silicon of N-type conductivity. In addition, a region 10 of the channel common to the source 1 is overdoped with P-type conductivity, the channel being of N-type conductivity in the example selected.
The floating gate 9 is negatively charged with hot electrons 6 and then positively charged with hot holes 11. ;~
This result may be obtained for example by applying a positive voltage to the drain for injecting electrons into the floating g~te or to the source for injecting holes, given suitable polarities of the control gate 3. ~ ~

:
11 : ' ~`:

~4~

This technique, which is based on the successive in~ection of '~ot" holes or electrons, generally leads t~ specialising the junctions or, as shown in Fig. 2, merely to localising an overdoped region of P+-type conductivity in the N-channel so as to facilitate the generation of the hot carriers.
It is the formation of this overdoped region in the channel of the transistor which determines the erasing of the content and which, in conventional memories, requires additional etching and doping. The minimum surface area ~0 occupied by these regions is defined by that o~ the smallest etched opening and by the permitted positioning tolerance relative to the junction of the source. ;
Dimensions of 4 x 4 ~ for the opening seem today to represent a minimum which must not be exceeded if it is desired to maintain a latitude of ~ 1 ~ for positioning the . gate in relation to this region.
The proposed invention enables these operations to be eliminated and provides for the formation of locally overdoped regions automatically aligI~ed with the lateral .
parts of the channel of thememory transistor.
- . , The reduction in~these surfaces is accompanied by a reduction in the surface area of the memory point and, hence, by a possible increase in the~ complexity of the memory.
Fig. 3 shows in more~ detaiL a~transistor of the type ~ .
: .:
, -~L~7~65 1 corresponding to Fig. 2 seen in plan in Fig~ 3a, in SOCtiOII
along the axis aa' of the channel in Fig. 3b and in section along the axis bb' of the channel in Fig. 3c.
These Figures again show: -- the so~rce region 1 doped with N+-type conductivity, - the drain region 2 doped with N~-type conductivity, - the control gate 3, preferably of silicon, - the floating gate 9 preferably of silicon doped with N-type conductivity, - the insulating oxide layer 4, - the overdoped P+~ region 10 which locally reduces the voltage stability of the source 1 and which facilitates the injection of holes;towards the floating gate in the zone denoted by the reference T. By way of explanation, the zone E from which electrons are injected from the drain to the floating gate has also been sho~n, - a P~ insulating region 12 separates the transistors from one another in a P-type substrate.

This type of transistor is described, apart from some 3 ~ 2 minor details, in ~S Patents Nos. ~g~Ç~Z~-~INTEL) and 4,016,588 (NEC).
In this embodiment, the successive injections into the floating gate oE~electrons from the drain and of holes from the source are controlled; by the different dopings of the ~ ~7 ~ S

- 1 regions of the channel and by the polarities applied to the control gate. Numerous improvements, in particular a local reduction in the thickness of the oxide laye~ of the channel, may be made in order to ;mprove the avalanche conditions.
However, as shown in Fig. 39 the overdoped P region 10 occupies an important place in the channel and its asymmetrical positioning therein determines the charging, discharging and reading characteristics of the transistor, whilst the floating and control gates have a form and occupy a position that are symmetrical in relation to the channel.
In the proposed device, the asymmetry between the junction of the drain and the junction of the source emanates from the asymmetry in the covering of the floating gate by the control gate and the overdoped P region is obtained by virtue of the particular configuration adopted which is based on the use of a localised oxidation proces~
for growing the oxide layer 4 in a particular manner.
Figs. 4a, b and c clearly show the asymmetrical structure of a transistor according to the invention and hhve been drawn in sLIch a way that they may be compared one by ~-one with Figures 3a, b, c. -~
Under an index system comparable to that used in Fig~,3a, ;~
b, c, Figures 4a, b, c again show: -~
:-~ 5 1 - the N -type source region 21 - the N+-type drain region 22 - the control gate 23 - the floating gate 29 S - the insulating oxide layer 24 - the P doped region 20 which performs a function identical with that performed by the P overdoped region 10 in Fig. 3.
The difference between the known transistors and this transistor according to the invention is clearly apparent:
the asymmetry between the source and drain junctions emanates from the asymmetry between ~he gates and is ~
obtained during production as a consequence of this ~ .
asymmetry between the gates and not, as in the prior art, as the result of a particular diffusion. Thus, the asymmetry between the gates emanates from simple and precise etching operations in the corresponding layers of.~licon and it is these gates which act as masks, partly covering the source and the drain, during~the subsequent operations of diffusion of the implanted source and drain : : 20 layers. `
: By using the local oxidation process for growing the : ;
oxide layer 24, the P+ doped region;20 is not only : .~ ;
: automatically aligned with the diffusions of the source 21 and the drain 22 (~igs. 4a and 4b~, but also with the sides of~

- ~ ~

~L~4~a65 - 1 the channel, as shown in Fig. 4c~ The choice of the doping of this region enables it simultaneously to perform the normal functions of insulating the transistors from one another and the P++ overdoped region 10 of Fi~ 3a, b3 c.
The localisation of the regions where holes or electrons are injected is shown in Fig. 4a from the source (T~ and from the drain (E) respectively.
The considerable reduction and the localisation to the ~
sides of the channel of the regiors reserved for the injection ---10 of holes in a region complementary to the region reserved for the injection of electrons provide for extremely effective injection of the holes coupled with minimal ageing of the memory point. This is because the punctiform localisation ~ ) of the plasma generated during the avalanche of the 15 junctions provides for an improvement in the efficiency of~;
injection of the hot carriers and for a reduction in the degree of trapping in the gate dielectric which causes 'lfatigue" in this type of device. ?
~y virtue of the precision afforded by the process 20 according to the invention, which is higher than that afforded by known processes, it is possible to reduce the dimensions of the memory point transistor and, hence, to provide more . ~
memory points on one and the same semiconductor crystal and thus to increase the power of the memory circuits.

: :

65i - 1 The description of the production process will enable the structure of the memory point transistor according to the invention and the advantages associated therewith, p~rticularly in regard to production, to be better understood~
The production process used is based on the so-called local oxidation technique ~or LOCOS in short) and on the silicon gate technique. The LOCOS technique uses the masking of the thermal oxidation by a layer of silicon nitride, whilst the silicon gate technique uses the masking of the drain-source diffusion by a gate of polycrystalline silicon. The use in addition to these two techniques of ion implantation enables extremely satisfactory operation of the memory point to be obtained.
The embodiment described here by way of example is illustrated in Figures 5a to 5f, each Figure showing the device at the end of the phase.
Fig. 5a shows the device after etching of the layer of silicon nitride Si3N4 42 deposited on a layer of silica SiO2 41 obtained by the thermal oxidation of a substrate of P-type silicon ~100 ~ having a surface resistivity of from 6 to 12 ohms/cm. Thicknesses of the order of 700 Angstroms for the layer of silica and 100 Angstroms for the layer of silicon nitride are suitable for this application. The two P+ regions are obtained by implantation.

The first, I1, formed in the regions to be oxidised will -~y~

- 1 simultaneously define the doping of the field regions and of the lateral parts of the channel. The second implantation I2 enables a layer doped more heavily than the starting substrate to be formed. This doping is carried out without masking throughout the memory part of the circuit and enables the threshold voltage and breakdown voltage of the transistors to be controlled.
The relative doses of the implantations I1 and I2 are such that, in the finished device, the avalanche occurs in the central or lateral parts of the channel, according to the polarity of the control gate.
Boron doses of 1013 A/cm~ for I1 and of 10 2 A/cm2 for I2 enable variations in the threshold voltage of 5 V to be obtained for pulses comprised between 20 and 30 V and for times not exceeding 50 msec.
The increase in the ion dose of I1 leads to a reduction in the voltage required to obtain a positive charge on the floating gate. The increase in the ion dose of I2 leads to a reduction in the voltage required to obtain a negative charge - 20 on the floating gate. In every case, the lateral surface doping of the channel produced by I1 must exceed that resulting from I~ by a factor of at least 5 in order to provide the element with good reversibility. An exaggerated i~crease in the doping of I2 producing that of I1 would lead to unstable ~7~95 ~ 1 elements under the reading conditions.
Fig. 5b shows the diffusion inside the substrate of these P~ regions ~ter oxidation of the field regions 43 and 44. The surface zone comprised between the regions 43 and 44 is neither oxidised nor diffused in the Figure because the layer of nitride 42 acted as a mask during these operations.
In this central region, which is protected by the nitride, the boron emanating from the implantation I2 has progressed further.
Fig. 5c shows the structure after etching and N+ doping by implantation of the first silicon gate level deposited in the vapour phase. This operation may be carried out by the implantation of phosphorus. A dose of 1014 A/cm2 at 80 Kev through the 800 Angstroms of the SiO2 gate layer 45 is ideally suitable because it enables theJunction 46 to be situated in the region overdoped by I2 and the breakdown effect caused by the lateral parasitic NPN to be avoided, The gate 47, which defines the length of the channel) has a width of 6 d Fig. ~b diagrammatically illustrates the structure after the deposition, etching and doping of the second gate level 48 which is asymmetrical in relation to the ~loating gate 47.
The layer 49 insulating the two gates may be obtained either by thermal oxiclation of the first level or by the deposition o~ ~

1 9 , , ., .

':

1 silica obtained by decomposition in the vapour phase.
The second diffusion is masked by the second gate level from the side ~f the source 46 and by the first level from the side of the drain 50. This diffusion is more heavily doped and deeper than the first shown in Fig. Sb. In this way, the voltage stability of thedrain is higher than that of the source by virtue of the junction curvature This increases the asymm~try and pro tes the injection of holes from the source side and the injection of electrons from the drain side. In addition, this diffusion which is deeper than the overdoped region I2 ~akes it possible to reduce the parasitic capacity of the drain and source junctions in this part which is reserved for the contacts of the transistor.
15This is of course only possible if the width of the channel determined by the width of the floating gate reduced by the lateral penetrations of the first diffusion on the source side and of the second diffusion on the drain - side is sufficient to avoid breakdown of the transistor.
A depth of the order of 0.5 and 1,5 microns, respec tively, for the first and second diffusions enables devices with excellent operating characteristics to be produced.
The control gate 48 has to be wide enough to be abIe to be positioned astride the edge of the floating gate 47 , ~
; ' ':
~

7~S

~ 1 on the source side. A width of 8 microns enables the tolerances of this operation to be readily observed. The openings of the contacts situated in the plane of the section are also shown.
It can be seen from Fig. 5e that a layer 51 of silicon oxide doped with phosphorus is then deposited over the entire surface of the device and subsequently subjected to a flow treatment.
The opening of the contacts, which was previously effected during the operations shot~n in Fig. 5d is completed after the insulating layer has been subjected to the flow treatment.
This method prevents excessive enlargement of the contacts caused by the different composition of the two oxide layers.
A metallisation in vacuo followed by etching completes the production of the memory point transistor and creates the electrical contacts in the form of metallic bands 52 on the source 52, 53 on the drain and 54 on the control gate.
Fig, 5f is a section through this type of transistor taken along a plane perpendicular to the axis of the channel.
This Figure shows the metallisation 54 of the control gate 48, the floating gate 49 - as its name implies - not being connected to any connection or to any fixed potential.
The invention, of which the structure of the memory point transistor and the production process have been described, ~7L~6 5 ~ 1 benefits from the advantages inherent in floating gate devices, namely:
- high retention guaranteed by oxide layers approximately 1000 ~ thick between the substrate and the floating gate, - an erasing method which uses hot carriers similar to those used for writing and which enables equally thick oxide layers to be retained between the floating gate and the control gate, - punctiform localisation of the plasma producing the holes on erasure, improvement in injection efficiency and reduction in the fatigue caused by tr!apping in the silica, - a structure having two superposed gate levels, the first -a floating gate - being used for storing the charges and the second, which asymmetrically covers the floating gate, being used for control.ling the device in the three functions:
reading, writing, erasing, ;:~
: . , , - a self-aligned production process which enables the essential characteristics of the memory point to be obtained .
: . independently of positioning, - a process which enables components of reduced dimensions ~ ~;
and, hence, high-capacity non-volatile memories to be .; .
produced.

~ ~ 22 ;~

,

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An electrically erasable memory point com-prising in a substrate of semiconductor, a source region of a first conductivity type, heavily doped, a drain region of the first conductivity type, also heavily doped, said source region and drain region being separated by a channel region of a conductivity type opposite to the first conductivity type, with said channel region comprising a central strip ex-tending between the source region and drain region and two lateral strips more doped than the central strip and extending from the source region to the drain region on each side of the central strip, a floating gate of polycrystalline silicon above the channel region and insulated from the substrate by a thin insulating layer, and a control gate of polycrystalline silicon insulated from the floating gate and from the substrate by another thin insu-lating layer, said control gate overlapping the floating gate at least above one extremity thereof on the side of the source region.

2. A memory point as claimed in claim 1 wherein said lateral strips of the channel region are laterally limited by thick silicon oxide and extend under said thick oxide.

3. A method of manufacturing an elec-trically erasable memory element on a silicon sub-strate, comprising the following steps :
- forming a thin silicon oxide layer and thereafter a silicon nitride layer, and etching said nitride layer for constituting a mask for ion implantation of an impurity of a first conductivity type, - implanting said impurity, - making a localized oxidation of silicon outside the area covered by nitride, so that thick oxide walls surround the area covered by nitride and so that the said impurity be repelled by the thick oxide within the area covered by nitride, - removing nitride, - depositing a first layer of polycrystal-line silicon and etching it to make a floating gate approximately in the middle of the area which was previously covered by nitride, - doping, with an impurity of a second type of conductivity opposite to the first type, regions of silicon not covered by the floating gate, to form a source region and a drain region separated by a channel region covered by the floating gate, - forming an insulating layer above the polycrystalline silicon and depositing a second polycrystalline silicon layer to form a control gate covering part of the floating gate and overlapping said floating gate on the source side, - doping again, with an impurity of the second type, the regions of substrate not covered by the gates or by thick oxide, - forming source, drain and control gate contacts.

4. Integrated circuit comprising on a substrate of silicon a plurality of elements according to claims 1 or 2.