KR920001074B1 - 멀티레벨 축적구조를 사용하는 반도체 메모리 - Google Patents

멀티레벨 축적구조를 사용하는 반도체 메모리 Download PDF

Info

Publication number
KR920001074B1
KR920001074B1 KR1019840003829A KR840003829A KR920001074B1 KR 920001074 B1 KR920001074 B1 KR 920001074B1 KR 1019840003829 A KR1019840003829 A KR 1019840003829A KR 840003829 A KR840003829 A KR 840003829A KR 920001074 B1 KR920001074 B1 KR 920001074B1
Authority
KR
South Korea
Prior art keywords
line
voltage
row address
charge
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019840003829A
Other languages
English (en)
Korean (ko)
Other versions
KR850001612A (ko
Inventor
요시노부 나까고에
마사까즈 아오끼
마사시 호리구찌
가즈히로 시모히가시
신이찌 이께나가
Original Assignee
가부시끼가이샤 히다찌세이사꾸쇼
미다 가쓰시게
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 히다찌세이사꾸쇼, 미다 가쓰시게 filed Critical 가부시끼가이샤 히다찌세이사꾸쇼
Publication of KR850001612A publication Critical patent/KR850001612A/ko
Application granted granted Critical
Publication of KR920001074B1 publication Critical patent/KR920001074B1/ko
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
KR1019840003829A 1983-07-04 1984-07-03 멀티레벨 축적구조를 사용하는 반도체 메모리 Expired KR920001074B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP83-120364 1983-07-04
JP58120364A JPS6013398A (ja) 1983-07-04 1983-07-04 半導体多値記憶装置
JP58-120364 1983-07-04

Publications (2)

Publication Number Publication Date
KR850001612A KR850001612A (ko) 1985-03-30
KR920001074B1 true KR920001074B1 (ko) 1992-02-01

Family

ID=14784365

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840003829A Expired KR920001074B1 (ko) 1983-07-04 1984-07-03 멀티레벨 축적구조를 사용하는 반도체 메모리

Country Status (6)

Country Link
US (1) US4709350A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0130614B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS6013398A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR920001074B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1224567A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3485555D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3485595D1 (de) * 1983-12-23 1992-04-23 Hitachi Ltd Halbleiterspeicher mit einer speicherstruktur mit vielfachen pegeln.
FR2580421A1 (fr) * 1985-04-12 1986-10-17 Eurotechnique Sa Memoire morte programmable electriquement
JP2678062B2 (ja) * 1989-06-14 1997-11-17 キヤノン株式会社 光電変換装置
WO1992012518A1 (de) * 1991-01-09 1992-07-23 Siemens Aktiengesellschaft Speicherzellenanordnung und verfahren zu deren betrieb
US6002614A (en) 1991-02-08 1999-12-14 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US5218569A (en) 1991-02-08 1993-06-08 Banks Gerald J Electrically alterable non-volatile memory with n-bits per memory cell
JP2921812B2 (ja) * 1992-12-24 1999-07-19 シャープ株式会社 不揮発性半導体記憶装置
US5440505A (en) * 1994-01-21 1995-08-08 Intel Corporation Method and circuitry for storing discrete amounts of charge in a single memory element
US5515317A (en) * 1994-06-02 1996-05-07 Intel Corporation Addressing modes for a dynamic single bit per cell to multiple bit per cell memory
EP0763242B1 (en) * 1994-06-02 2001-07-11 Intel Corporation Sensing schemes for flash memory with multilevel cells
US6353554B1 (en) 1995-02-27 2002-03-05 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US5815434A (en) * 1995-09-29 1998-09-29 Intel Corporation Multiple writes per a single erase for a nonvolatile memory
US5701266A (en) * 1995-12-14 1997-12-23 Intel Corporation Programming flash memory using distributed learning methods
US5677869A (en) * 1995-12-14 1997-10-14 Intel Corporation Programming flash memory using strict ordering of states
US5729489A (en) * 1995-12-14 1998-03-17 Intel Corporation Programming flash memory using predictive learning methods
US5737265A (en) * 1995-12-14 1998-04-07 Intel Corporation Programming flash memory using data stream analysis
JP3613622B2 (ja) * 1996-09-27 2005-01-26 株式会社日立製作所 半導体メモリ
US5761114A (en) * 1997-02-19 1998-06-02 International Business Machines Corporation Multi-level storage gain cell with stepline
JPH11178383A (ja) * 1997-12-04 1999-07-02 Toshiba Corp 電動機の制御装置
US6279133B1 (en) 1997-12-31 2001-08-21 Kawasaki Steel Corporation Method and apparatus for significantly improving the reliability of multilevel memory architecture
JP2000116199A (ja) 1998-10-01 2000-04-21 Toshiba Corp 電動機制御装置
KR20030003312A (ko) * 2001-06-30 2003-01-10 주식회사 하이닉스반도체 다중 비트 커패시터를 갖는 반도체 메모리
JP2009009641A (ja) * 2007-06-27 2009-01-15 Elpida Memory Inc 半導体記憶装置及びその読み出し方法
US8174923B2 (en) * 2007-11-08 2012-05-08 Rambus Inc. Voltage-stepped low-power memory device
US8773925B2 (en) 2010-02-23 2014-07-08 Rambus Inc. Multilevel DRAM
WO2011114905A1 (en) * 2010-03-19 2011-09-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device
US10985162B2 (en) 2018-12-14 2021-04-20 John Bennett System for accurate multiple level gain cells

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024512A (en) * 1975-06-16 1977-05-17 Fairchild Camera And Instrument Corporation Line-addressable random-access memory
US4300210A (en) * 1979-12-27 1981-11-10 International Business Machines Corp. Calibrated sensing system
US4459609A (en) * 1981-09-14 1984-07-10 International Business Machines Corporation Charge-stabilized memory

Also Published As

Publication number Publication date
JPS6013398A (ja) 1985-01-23
CA1224567A (en) 1987-07-21
KR850001612A (ko) 1985-03-30
JPH0557679B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-08-24
EP0130614A3 (en) 1988-08-31
DE3485555D1 (de) 1992-04-16
US4709350A (en) 1987-11-24
EP0130614A2 (en) 1985-01-09
EP0130614B1 (en) 1992-03-11

Similar Documents

Publication Publication Date Title
KR920001074B1 (ko) 멀티레벨 축적구조를 사용하는 반도체 메모리
US6982918B2 (en) Data storage device and refreshing method for use with such device
US4661929A (en) Semiconductor memory having multiple level storage structure
KR930004626B1 (ko) 불휘발성 기억장치
US6614686B1 (en) Nonvolatile memory circuit for recording multiple bit information
KR100650244B1 (ko) 게이트 다이오드 메모리 셀, 메모리 어레이 및 게이트다이오드 메모리 셀에 대한 기록 방법
JP4164241B2 (ja) 半導体装置
KR100263084B1 (ko) 강유전성 회로를 위한 기준전압의 동적 조정
US5294819A (en) Single-transistor cell EEPROM array for analog or digital storage
WO2005078732A1 (en) Electronic memory with tri-level cell pair
CN1615526A (zh) 用于具有邻近位预先充电的闪速eprom阵列的虚拟接地读取的源极侧感测结构
EP1120791A1 (en) Semiconductor device
US3824564A (en) Integrated threshold mnos memory with decoder and operating sequence
US3876993A (en) Random access memory cell
US4882706A (en) Data storage element and memory structures employing same
US3706079A (en) Three-line cell for random-access integrated circuit memory
JP4643092B2 (ja) 改良型多層ｄｒａｍ
KR930007280B1 (ko) 전하 전송형 전압증폭기를 갖는 반도체 메모리
JP3741231B2 (ja) 不揮発性記憶装置
US6072713A (en) Data storage circuit using shared bit line and method therefor
JPS63276791A (ja) 多値メモリの構成方法
US6195284B1 (en) Semiconductor memory device
CN109256157B (zh) 多值存储器的实现方法
JP4373464B2 (ja) 半導体装置
US6021064A (en) Layout for data storage circuit using shared bit line and method therefor

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

St.27 status event code: A-2-2-Q10-Q13-nap-PG1605

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

FPAY Annual fee payment

Payment date: 20020124

Year of fee payment: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20030202

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20030202

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000