KR910020871A - 반도체 소자용 전극, 전극을 갖춘 반도체장치 및 그 제조방법 - Google Patents
반도체 소자용 전극, 전극을 갖춘 반도체장치 및 그 제조방법 Download PDFInfo
- Publication number
- KR910020871A KR910020871A KR1019910008246A KR910008246A KR910020871A KR 910020871 A KR910020871 A KR 910020871A KR 1019910008246 A KR1019910008246 A KR 1019910008246A KR 910008246 A KR910008246 A KR 910008246A KR 910020871 A KR910020871 A KR 910020871A
- Authority
- KR
- South Korea
- Prior art keywords
- electrode
- length
- contact hole
- semiconductor device
- semiconductor
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004020 conductor Substances 0.000 claims 4
- 229910052739 hydrogen Inorganic materials 0.000 claims 4
- 238000000034 method Methods 0.000 claims 4
- -1 alkylaluminum hydride Chemical class 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- TUTOKIOKAWTABR-UHFFFAOYSA-N dimethylalumane Chemical group C[AlH]C TUTOKIOKAWTABR-UHFFFAOYSA-N 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 230000001376 precipitating effect Effects 0.000 claims 1
- 238000001556 precipitation Methods 0.000 claims 1
- 238000006557 surface reaction Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도A는 내지 제1E도는 본 발명에 따른 반도체용 전극의 구조를 예시하는 개략도, 제2도 내지 제5도는 본 발명에 따른 반도체 장치의 준비를 위하여 적합한 준비장치를 예시하는 계략도.
Claims (9)
- 실질적으로 사각형기둥의 형상인 반도체소자의 반도체영역에 직접 접속되는 반도체 소자용 전극이 상기 전극에서 반도체 영역과 접촉하는 표면의 한변의 길이가 L, 다른변의 길이는 W 및 상기 표면에 실질적으로 수직으로 가로지르는 방향으로의 길이가 H로서 정의될 때, 상기 L, W, H는 L > H >W의 관계를 만족하는 것을 특징으로 하는 반도체 소자용전극.
- 제1항에 있어서, 상기 전극이 단결정질 Aℓ을 포함하는 것을 특징으로 하는 반도체 소자용전극.
- 제1항에 있어서, 상기 전극이 주로 Aℓ으로 구성되는 도체를 포함하는 것을 특징으로 하는 반도체 소자용전극.
- 반도체 기판의 주표면상에 형성된 반도체소자 및 상기 주표면상에 제공되는 절연막의 접촉홀을 통하여 접속되는 전극을 포함하며, 상기 접촉홀은 실질적으로 사각형의 개구를 가지며 상기 전극에서 반도체영역과 접촉하는 표면의 한변의 길이가, L, 다른변의 길이는 W 및 상기 표면에 실질적으로 수직으로 가로지르는 방향으로의 길이가 H로서 정의될 때, 상기 L, W, H는 L > H >W의 관계를 만족하는 것을 특징으로 하는 반도체장치.
- 제4항에 있어서, 상기 접촉홀내의 전극이 단결정질 Aℓ을 포함하는 것을 특징으로 하는 반도체장치.
- 제4항에 있어서, 상기 접촉홀내의 전극이 주로 Aℓ으로 구성되는 도체를 포함하는 것을 특징으로 하는 반도체 장치.
- 반도체기판의 주표면상에 형성된 반도체소자 및 상기 주표면상에 제공되는 절연막의 접촉홀을 통하여 접속되는 전극을 포함하는 반도체 장치를 준비하기 위한 방법에 있어서, 상기 접촉홀에 개구의 한변의 길이가 L, 다른변의 길이는 W 및 상기 표면에 실질적으로 수직으로 가로지르는 방향으로의 길이가 H로서 정의될때, 상기 L, W, H는 L > H >W의 관계를 만족하는 접촉홀을 형성하는 단계; 및 적어도 알킬알루미늄 수소화물 및 수소의 개스를 활용하는 CVD법에 의하여 상기 접촉홀내에 Aℓ또는 주로 Aℓ으로 구성된 도체를 침전시키는 단계를 포함하는 것을 특징으로 하는 반도체장치를 준비하기 위한 방법.
- 제7항에 있어서, 상기 알킬알루미늄 수소화물이 디메틸알루미늄 수소화물인 것을 특징으로 하는 반도체장치를 준비하기 위한 방법.
- 제7항에 있어서, 상기 접촉홀을 형성하는 단계에 있어서, 전자증여 표면이 상기 홀내에서 노출되고 또한 상기 침전의 단계에서 상기 Aℓ또는 주로 Aℓ으로 구성되는 도체가 상기 전자증여 표면상에 표면반응을 통하여 선택적으로 코팅되는 것을 특징으로 하는 반도체장치를 준비하기 위한 방법.※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2-143732 | 1990-05-31 | ||
JP2143732A JPH0437067A (ja) | 1990-05-31 | 1990-05-31 | 半導体素子用電極及び該電極を有する半導体装置及びその製造方法 |
JP90-143732 | 1990-05-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910020871A true KR910020871A (ko) | 1991-12-20 |
KR950000207B1 KR950000207B1 (ko) | 1995-01-11 |
Family
ID=15345724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910008246A KR950000207B1 (ko) | 1990-05-31 | 1991-05-22 | 반도체소자용 전극, 전극을 갖춘 반도체장치 및 그 제조방법 |
Country Status (6)
Country | Link |
---|---|
US (2) | US5233224A (ko) |
EP (1) | EP0463731A1 (ko) |
JP (1) | JPH0437067A (ko) |
KR (1) | KR950000207B1 (ko) |
CN (2) | CN1027946C (ko) |
MY (1) | MY108561A (ko) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04309248A (ja) * | 1991-04-08 | 1992-10-30 | Nec Corp | 半導体装置 |
US5580808A (en) * | 1992-07-30 | 1996-12-03 | Canon Kabushiki Kaisha | Method of manufacturing a ROM device having contact holes treated with hydrogen atoms and energy beam |
JP3334911B2 (ja) * | 1992-07-31 | 2002-10-15 | キヤノン株式会社 | パターン形成方法 |
KR970001883B1 (ko) * | 1992-12-30 | 1997-02-18 | 삼성전자 주식회사 | 반도체장치 및 그 제조방법 |
US5571751A (en) * | 1994-05-09 | 1996-11-05 | National Semiconductor Corporation | Interconnect structures for integrated circuits |
US5464794A (en) * | 1994-05-11 | 1995-11-07 | United Microelectronics Corporation | Method of forming contact openings having concavo-concave shape |
EP0703611B1 (en) * | 1994-08-31 | 2007-05-02 | Texas Instruments Incorporated | Method for insulating metal leads using a low dielectric constant material, and structures formed therewith |
US6069370A (en) * | 1997-03-26 | 2000-05-30 | Nec Corporation | Field-effect transistor and fabrication method thereof and image display apparatus |
US6054769A (en) * | 1997-01-17 | 2000-04-25 | Texas Instruments Incorporated | Low capacitance interconnect structures in integrated circuits having an adhesion and protective overlayer for low dielectric materials |
US5818111A (en) * | 1997-03-21 | 1998-10-06 | Texas Instruments Incorporated | Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials |
US6332835B1 (en) | 1997-11-20 | 2001-12-25 | Canon Kabushiki Kaisha | Polishing apparatus with transfer arm for moving polished object without drying it |
US6965165B2 (en) | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US7381642B2 (en) | 2004-09-23 | 2008-06-03 | Megica Corporation | Top layers of metal for integrated circuits |
US7405149B1 (en) * | 1998-12-21 | 2008-07-29 | Megica Corporation | Post passivation method for semiconductor chip or wafer |
US7335556B2 (en) * | 2004-06-14 | 2008-02-26 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
DE102005041099A1 (de) * | 2005-08-30 | 2007-03-29 | Osram Opto Semiconductors Gmbh | LED-Chip mit Glasbeschichtung und planarer Aufbau- und Verbindungstechnik |
JP2008060532A (ja) * | 2006-08-04 | 2008-03-13 | Seiko Epson Corp | 半導体装置 |
Family Cites Families (19)
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US3847687A (en) * | 1972-11-15 | 1974-11-12 | Motorola Inc | Methods of forming self aligned transistor structure having polycrystalline contacts |
JPS5459080A (en) * | 1977-10-19 | 1979-05-12 | Nec Corp | Semiconductor device |
GB2038883B (en) | 1978-11-09 | 1982-12-08 | Standard Telephones Cables Ltd | Metallizing semiconductor devices |
US4438450A (en) * | 1979-11-30 | 1984-03-20 | Bell Telephone Laboratories, Incorporated | Solid state device with conductors having chain-shaped grain structure |
JPS58176937A (ja) | 1982-04-09 | 1983-10-17 | Fujitsu Ltd | 微細パタ−ン |
US4515654A (en) * | 1982-07-06 | 1985-05-07 | General Electric Company | Method for making semiconductor devices utilizing eutectic masks |
US4673960A (en) * | 1982-12-09 | 1987-06-16 | Cornell Research Foundation, Inc. | Fabrication of metal lines for semiconductor devices |
JPS62123716A (ja) | 1985-11-22 | 1987-06-05 | Nec Corp | 半導体装置の製造方法 |
US4920070A (en) * | 1987-02-19 | 1990-04-24 | Fujitsu Limited | Method for forming wirings for a semiconductor device by filling very narrow via holes |
KR910006164B1 (ko) * | 1987-03-18 | 1991-08-16 | 가부시키가이샤 도시바 | 박막형성방법과 그 장치 |
US4878770A (en) * | 1987-09-09 | 1989-11-07 | Analog Devices, Inc. | IC chips with self-aligned thin film resistors |
JPH01198475A (ja) | 1988-02-02 | 1989-08-10 | Anelva Corp | 薄膜作製方法 |
US5001081A (en) * | 1988-01-19 | 1991-03-19 | National Semiconductor Corp. | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide |
US5468989A (en) * | 1988-06-02 | 1995-11-21 | Hitachi, Ltd. | Semiconductor integrated circuit device having an improved vertical bipolar transistor structure |
JPH0623429B2 (ja) | 1988-07-28 | 1994-03-30 | 日電アネルバ株式会社 | シリコン基板上にアルミニウムの平滑な薄膜を作製する方法とそれを用いた光学的反射鏡 |
JPH02185026A (ja) * | 1989-01-11 | 1990-07-19 | Nec Corp | Al薄膜の選択的形成方法 |
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EP0390606A3 (en) * | 1989-03-31 | 1991-10-09 | Canon Kabushiki Kaisha | Semiconductor device having transistor improved in emitter region and/or base electrode |
JP2721023B2 (ja) * | 1989-09-26 | 1998-03-04 | キヤノン株式会社 | 堆積膜形成法 |
-
1990
- 1990-05-31 JP JP2143732A patent/JPH0437067A/ja active Pending
-
1991
- 1991-05-14 US US07/699,596 patent/US5233224A/en not_active Expired - Lifetime
- 1991-05-22 EP EP91304657A patent/EP0463731A1/en not_active Ceased
- 1991-05-22 KR KR1019910008246A patent/KR950000207B1/ko not_active IP Right Cessation
- 1991-05-29 MY MYPI91000935A patent/MY108561A/en unknown
- 1991-05-31 CN CN91103577A patent/CN1027946C/zh not_active Expired - Fee Related
-
1993
- 1993-10-20 CN CN93119316A patent/CN1037301C/zh not_active Expired - Fee Related
-
1994
- 1994-06-10 US US08/258,370 patent/US6218223B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5233224A (en) | 1993-08-03 |
JPH0437067A (ja) | 1992-02-07 |
KR950000207B1 (ko) | 1995-01-11 |
MY108561A (en) | 1996-10-31 |
CN1027946C (zh) | 1995-03-15 |
CN1037301C (zh) | 1998-02-04 |
CN1106163A (zh) | 1995-08-02 |
US6218223B1 (en) | 2001-04-17 |
EP0463731A1 (en) | 1992-01-02 |
CN1056954A (zh) | 1991-12-11 |
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