KR900015326A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR900015326A
KR900015326A KR1019900003421A KR900003421A KR900015326A KR 900015326 A KR900015326 A KR 900015326A KR 1019900003421 A KR1019900003421 A KR 1019900003421A KR 900003421 A KR900003421 A KR 900003421A KR 900015326 A KR900015326 A KR 900015326A
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KR
South Korea
Prior art keywords
functional
functional block
memory cell
cell array
formed directly
Prior art date
Application number
KR1019900003421A
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English (en)
Other versions
KR930002285B1 (ko
Inventor
마사시 와다
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR900015326A publication Critical patent/KR900015326A/ko
Application granted granted Critical
Publication of KR930002285B1 publication Critical patent/KR930002285B1/ko

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • H10B20/60Peripheral circuit regions
    • H10B20/65Peripheral circuit regions of memory structures of the ROM only type
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

내용 없음.

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 개념도.
제2도 (A)내지 제2도 (C)는 본 발명에 따른 1실시예의 공정단면도.

Claims (4)

  1. 반도체기판(100)과, 이 반도체기판(100)상에 직접 형성되어 데이터처리를 행하는 제1기능블럭(202), 데이터처리를 행할 때 필요한 정보를 미리 기억시키기 위한 제2기능블럭(206,302)릍 구비하고, 그중 상기 제2기능블럭은 복수의 메모리셀을 갖춘 메모리셀어레이(302)와, 이 메모리셀어레이(302)로 부터의 데이터를 독출하는 기능소자부분(206)을 구비한 것이고, 상기 기능소자부분(206)은 상기 반도체 기판(100) 상에 직접 형성되어 있는 것이며, 상기 메모리셀어레이(302)는 상기 제1기능블럭(202) 및 상기 기능소자부본(206)의 상부에 절연 보호막(110)을 매개로 형성되어 있는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 제1기능블럭(202)은 CPU이고, 상기 제2기능블럭(206,302)은 마스크 ROM인 것을 특징으로 하는 반도체 장치.
  3. 제1항에 있어서, 상기 반도체기간(100)상에 직접 형성된 상기 제1기능블럭(202)과, 이와 동일하게 상기 반도체기판(100)상에 직접형성된 상기 제2기능블럭(206,302)의 기능소자부분은 각각 트랜지스터를 구비하여 구성된 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 상기 메모리셀어레이(302)는 상기 데이터에 의해 각각 선택되는 여러개의 X방향도전선(112)과 여러개의 Y방향도전선(115)을 구비하고 있고, 이들 X방향 및 Y방향도전선(112,115)은 절연막(113)을 매개로 상하로 형성되며 입체교차되어 있는 것을 특징으로 하는 반도체 장치.
    ※참고사항:최초출원 내용에 의하여 공개하는 것임.
KR1019900003421A 1989-03-14 1990-03-14 반도체장치 KR930002285B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1061559A JP2778977B2 (ja) 1989-03-14 1989-03-14 半導体装置及びその製造方法
JP01-061559 1989-03-14
JP1-61559 1989-03-14

Publications (2)

Publication Number Publication Date
KR900015326A true KR900015326A (ko) 1990-10-26
KR930002285B1 KR930002285B1 (ko) 1993-03-29

Family

ID=13174590

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900003421A KR930002285B1 (ko) 1989-03-14 1990-03-14 반도체장치

Country Status (4)

Country Link
US (1) US5521417A (ko)
EP (2) EP0387834A3 (ko)
JP (1) JP2778977B2 (ko)
KR (1) KR930002285B1 (ko)

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CN111446246A (zh) * 2016-03-07 2020-07-24 杭州海存信息技术有限公司 兼具数据分析功能的存储器

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US5874340A (en) * 1996-07-17 1999-02-23 Advanced Micro Devices, Inc. Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls
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US5677224A (en) * 1996-09-03 1997-10-14 Advanced Micro Devices, Inc. Method of making asymmetrical N-channel and P-channel devices
US5648286A (en) * 1996-09-03 1997-07-15 Advanced Micro Devices, Inc. Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region
US5890199A (en) * 1996-10-21 1999-03-30 Ramtron International Corporation Data processor incorporating a ferroelectric memory array selectably configurable as read/write and read only memory
US6027978A (en) * 1997-01-28 2000-02-22 Advanced Micro Devices, Inc. Method of making an IGFET with a non-uniform lateral doping profile in the channel region
US5849622A (en) * 1997-03-07 1998-12-15 Advanced Micro Devices, Inc. Method of forming a source implant at a contact masking step of a process flow
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US5923982A (en) * 1997-04-21 1999-07-13 Advanced Micro Devices, Inc. Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps
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US5904529A (en) * 1997-08-25 1999-05-18 Advanced Micro Devices, Inc. Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate
US6096588A (en) * 1997-11-01 2000-08-01 Advanced Micro Devices, Inc. Method of making transistor with selectively doped channel region for threshold voltage control
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KR20050104652A (ko) * 2004-04-29 2005-11-03 삼성에스디아이 주식회사 전자 방출 표시 장치 및 그 구동 방법
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Publication number Priority date Publication date Assignee Title
CN111446246A (zh) * 2016-03-07 2020-07-24 杭州海存信息技术有限公司 兼具数据分析功能的存储器
CN111446246B (zh) * 2016-03-07 2023-04-07 杭州海存信息技术有限公司 兼具数据分析功能的存储器

Also Published As

Publication number Publication date
EP0387834A3 (en) 1991-07-24
JP2778977B2 (ja) 1998-07-23
EP0387834A2 (en) 1990-09-19
US5521417A (en) 1996-05-28
EP1215727A3 (en) 2007-05-02
JPH02239652A (ja) 1990-09-21
EP1215727A2 (en) 2002-06-19
KR930002285B1 (ko) 1993-03-29

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