KR900005785B1 - 평탄성 박막의 제조방법 - Google Patents

평탄성 박막의 제조방법 Download PDF

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Publication number
KR900005785B1
KR900005785B1 KR1019860003683A KR860003683A KR900005785B1 KR 900005785 B1 KR900005785 B1 KR 900005785B1 KR 1019860003683 A KR1019860003683 A KR 1019860003683A KR 860003683 A KR860003683 A KR 860003683A KR 900005785 B1 KR900005785 B1 KR 900005785B1
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KR
South Korea
Prior art keywords
thin film
substrate
film
charged particles
electrode
Prior art date
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Expired
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KR1019860003683A
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English (en)
Korean (ko)
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KR860009480A (ko
Inventor
카즈요시 카모시다
히로아끼 나까무라
다까오 아마자와
Original Assignee
닛뽄덴신덴와 가부시끼가이샤
신도우 히산
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Filing date
Publication date
Priority claimed from JP60099505A external-priority patent/JPS61261472A/ja
Priority claimed from JP60209741A external-priority patent/JPS6269534A/ja
Application filed by 닛뽄덴신덴와 가부시끼가이샤, 신도우 히산 filed Critical 닛뽄덴신덴와 가부시끼가이샤
Publication of KR860009480A publication Critical patent/KR860009480A/ko
Application granted granted Critical
Publication of KR900005785B1 publication Critical patent/KR900005785B1/ko
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation

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  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019860003683A 1985-05-13 1986-05-12 평탄성 박막의 제조방법 Expired KR900005785B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP60-99505 1985-05-13
JP99505 1985-05-13
JP60099505A JPS61261472A (ja) 1985-05-13 1985-05-13 バイアススパツタ法およびその装置
JP209741 1985-09-20
JP60-209741 1985-09-20
JP60209741A JPS6269534A (ja) 1985-09-20 1985-09-20 平坦性薄膜の形成方法

Publications (2)

Publication Number Publication Date
KR860009480A KR860009480A (ko) 1986-12-23
KR900005785B1 true KR900005785B1 (ko) 1990-08-11

Family

ID=26440635

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860003683A Expired KR900005785B1 (ko) 1985-05-13 1986-05-12 평탄성 박막의 제조방법

Country Status (5)

Country Link
US (1) US4816126A (https=)
EP (2) EP0544648B1 (https=)
KR (1) KR900005785B1 (https=)
CA (1) CA1247464A (https=)
DE (2) DE3650612T2 (https=)

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JP2602276B2 (ja) * 1987-06-30 1997-04-23 株式会社日立製作所 スパツタリング方法とその装置
FR2634317A1 (fr) * 1988-07-12 1990-01-19 Philips Nv Procede pour fabriquer un dispositif semiconducteur ayant au moins un niveau de prise de contact a travers des ouvertures de contact de petites dimensions
US5231055A (en) * 1989-01-13 1993-07-27 Texas Instruments Incorporated Method of forming composite interconnect system
US5419822A (en) * 1989-02-28 1995-05-30 Raytheon Company Method for applying a thin adherent layer
US4994162A (en) * 1989-09-29 1991-02-19 Materials Research Corporation Planarization method
JP2758948B2 (ja) * 1989-12-15 1998-05-28 キヤノン株式会社 薄膜形成方法
DE69129081T2 (de) * 1990-01-29 1998-07-02 Varian Associates Gerät und Verfahren zur Niederschlagung durch einen Kollimator
US5108570A (en) * 1990-03-30 1992-04-28 Applied Materials, Inc. Multistep sputtering process for forming aluminum layer over stepped semiconductor wafer
US5011793A (en) * 1990-06-19 1991-04-30 Nihon Shinku Gijutsu Kabushiki Kaisha Vacuum deposition using pressurized reflow process
DE4028776C2 (de) * 1990-07-03 1994-03-10 Samsung Electronics Co Ltd Verfahren zur Bildung einer metallischen Verdrahtungsschicht und Füllen einer Kontaktöffnung in einem Halbleiterbauelement
KR950009939B1 (ko) * 1990-11-30 1995-09-01 가부시끼가이샤 히다찌세이사꾸쇼 박막 형성 방법 및 그에 의해 형성된 반도체 장치
EP0491503A3 (en) * 1990-12-19 1992-07-22 AT&T Corp. Method for depositing metal
US5171412A (en) * 1991-08-23 1992-12-15 Applied Materials, Inc. Material deposition method for integrated circuit manufacturing
US6127730A (en) * 1992-05-26 2000-10-03 Texas Instruments Incorporated Composite metal films for severe topology interconnects
JPH07105441B2 (ja) * 1992-11-30 1995-11-13 日本電気株式会社 半導体装置の製造方法
US5360524A (en) * 1993-04-13 1994-11-01 Rudi Hendel Method for planarization of submicron vias and the manufacture of semiconductor integrated circuits
US5380414A (en) * 1993-06-11 1995-01-10 Applied Materials, Inc. Shield and collimator pasting deposition chamber with a wafer support periodically used as an acceptor
JP3382031B2 (ja) * 1993-11-16 2003-03-04 株式会社東芝 半導体装置の製造方法
US5639357A (en) * 1994-05-12 1997-06-17 Applied Materials Synchronous modulation bias sputter method and apparatus for complete planarization of metal films
KR960015719A (ko) * 1994-10-12 1996-05-22 이온 충돌을 이용하여 반도체 기판상에 평탄한 층을 형성하기 위한 방법 및 장치
EP0735577A3 (en) * 1994-12-14 1997-04-02 Applied Materials Inc Separation process and facility therefor
US5807467A (en) 1996-01-22 1998-09-15 Micron Technology, Inc. In situ preclean in a PVD chamber with a biased substrate configuration
JP3523962B2 (ja) * 1996-05-21 2004-04-26 アネルバ株式会社 スパッタリング装置及びホール内へのスパッタリングによる薄膜作成方法
JP3514408B2 (ja) * 1996-09-12 2004-03-31 キヤノン株式会社 透明導電膜をスパッタ形成する方法
US5961793A (en) * 1996-10-31 1999-10-05 Applied Materials, Inc. Method of reducing generation of particulate matter in a sputtering chamber
TW358964B (en) 1996-11-21 1999-05-21 Applied Materials Inc Method and apparatus for improving sidewall coverage during sputtering in a chamber having an inductively coupled plasma
US6451179B1 (en) 1997-01-30 2002-09-17 Applied Materials, Inc. Method and apparatus for enhancing sidewall coverage during sputtering in a chamber having an inductively coupled plasma
US6605197B1 (en) * 1997-05-13 2003-08-12 Applied Materials, Inc. Method of sputtering copper to fill trenches and vias
US6042700A (en) * 1997-09-15 2000-03-28 Applied Materials, Inc. Adjustment of deposition uniformity in an inductively coupled plasma source
US6023038A (en) * 1997-09-16 2000-02-08 Applied Materials, Inc. Resistive heating of powered coil to reduce transient heating/start up effects multiple loadlock system
US6177350B1 (en) 1998-04-14 2001-01-23 Applied Materials, Inc. Method for forming a multilayered aluminum-comprising structure on a substrate
US6287977B1 (en) 1998-07-31 2001-09-11 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
JP4458740B2 (ja) * 2002-09-13 2010-04-28 株式会社アルバック バイアススパッタ成膜方法及びバイアススパッタ成膜装置
US20080173538A1 (en) * 2007-01-19 2008-07-24 Kim Sun-Oo Method and apparatus for sputtering
KR102152811B1 (ko) 2013-11-06 2020-09-07 어플라이드 머티어리얼스, 인코포레이티드 Ｄｃ 바이어스 변조에 의한 입자 발생 억제기

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3451912A (en) * 1966-07-15 1969-06-24 Ibm Schottky-barrier diode formed by sputter-deposition processes
US3661761A (en) * 1969-06-02 1972-05-09 Ibm Rf sputtering apparatus for promoting resputtering of film during deposition
FR2119930B1 (https=) * 1970-12-31 1974-08-19 Ibm
US3868723A (en) * 1973-06-29 1975-02-25 Ibm Integrated circuit structure accommodating via holes
US4007103A (en) * 1975-10-14 1977-02-08 Ibm Corporation Planarizing insulative layers by resputtering
US4035276A (en) * 1976-04-29 1977-07-12 Ibm Corporation Making coplanar layers of thin films
GB2023926B (en) * 1978-06-22 1983-03-16 Western Electric Co Conductors for semiconductor devices
DE2937993A1 (de) * 1979-09-20 1981-04-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-halbleiterschaltungen nach der silizium-gate-technologie
US4336118A (en) * 1980-03-21 1982-06-22 Battelle Memorial Institute Methods for making deposited films with improved microstructures
US4327477A (en) * 1980-07-17 1982-05-04 Hughes Aircraft Co. Electron beam annealing of metal step coverage
US4510173A (en) * 1983-04-25 1985-04-09 Kabushiki Kaisha Toshiba Method for forming flattened film
JPH069199B2 (ja) * 1984-07-18 1994-02-02 株式会社日立製作所 配線構造体およびその製造方法

Also Published As

Publication number Publication date
DE3689388T2 (de) 1994-05-26
EP0544648A3 (https=) 1994-02-16
EP0202572A3 (en) 1989-09-27
KR860009480A (ko) 1986-12-23
DE3650612D1 (de) 1997-05-15
EP0202572A2 (en) 1986-11-26
DE3650612T2 (de) 1997-08-21
EP0202572B1 (en) 1993-12-15
EP0544648A2 (en) 1993-06-02
US4816126A (en) 1989-03-28
CA1247464A (en) 1988-12-28
EP0544648B1 (en) 1997-04-09
DE3689388D1 (de) 1994-01-27

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