KR960015719A - 이온 충돌을 이용하여 반도체 기판상에 평탄한 층을 형성하기 위한 방법 및 장치 - Google Patents

이온 충돌을 이용하여 반도체 기판상에 평탄한 층을 형성하기 위한 방법 및 장치 Download PDF

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Publication number
KR960015719A
KR960015719A KR1019950034210A KR19950034210A KR960015719A KR 960015719 A KR960015719 A KR 960015719A KR 1019950034210 A KR1019950034210 A KR 1019950034210A KR 19950034210 A KR19950034210 A KR 19950034210A KR 960015719 A KR960015719 A KR 960015719A
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KR
South Korea
Prior art keywords
forming
semiconductor substrate
flat layer
ion bombardment
bombardment
Prior art date
Application number
KR1019950034210A
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English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR960015719A publication Critical patent/KR960015719A/ko

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Classifications

    • H01L21/205—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
KR1019950034210A 1994-10-12 1995-10-06 이온 충돌을 이용하여 반도체 기판상에 평탄한 층을 형성하기 위한 방법 및 장치 KR960015719A (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US32209594A 1994-10-12 1994-10-12

Publications (1)

Publication Number Publication Date
KR960015719A true KR960015719A (ko) 1996-05-22

Family

ID=23253390

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950034210A KR960015719A (ko) 1994-10-12 1995-10-06 이온 충돌을 이용하여 반도체 기판상에 평탄한 층을 형성하기 위한 방법 및 장치

Country Status (3)

Country Link
EP (1) EP0707339A3 (ko)
JP (1) JPH08213322A (ko)
KR (1) KR960015719A (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100411144B1 (ko) * 2002-02-26 2003-12-24 서울대학교 공과대학 교육연구재단 아르곤-수소 플라즈마를 이용한 무플럭스 솔더 범프의 리플로우 방법
KR101373733B1 (ko) * 2007-03-08 2014-03-14 삼성전자 주식회사 절연물 증착을 사용한 집적 회로 구조 형성 방법 및 절연물갭 필링 기술

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104596A (en) * 1998-04-21 2000-08-15 Applied Materials, Inc. Apparatus for retaining a subtrate in a semiconductor wafer processing system and a method of fabricating same
JP3069336B2 (ja) * 1998-12-04 2000-07-24 キヤノン販売株式会社 成膜装置
US10304732B2 (en) * 2017-09-21 2019-05-28 Applied Materials, Inc. Methods and apparatus for filling substrate features with cobalt
CN112635305A (zh) * 2020-11-24 2021-04-09 武汉新芯集成电路制造有限公司 半导体器件及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0202572B1 (en) * 1985-05-13 1993-12-15 Nippon Telegraph And Telephone Corporation Method for forming a planarized aluminium thin film
US4756810A (en) 1986-12-04 1988-07-12 Machine Technology, Inc. Deposition and planarizing methods and apparatus
JPH07105441B2 (ja) * 1992-11-30 1995-11-13 日本電気株式会社 半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100411144B1 (ko) * 2002-02-26 2003-12-24 서울대학교 공과대학 교육연구재단 아르곤-수소 플라즈마를 이용한 무플럭스 솔더 범프의 리플로우 방법
KR101373733B1 (ko) * 2007-03-08 2014-03-14 삼성전자 주식회사 절연물 증착을 사용한 집적 회로 구조 형성 방법 및 절연물갭 필링 기술

Also Published As

Publication number Publication date
EP0707339A3 (en) 1997-10-08
JPH08213322A (ja) 1996-08-20
EP0707339A2 (en) 1996-04-17

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