KR900005702A - 프로그램 가능한 입력/출력회로 및 프로그램 가능한 논리소자 - Google Patents
프로그램 가능한 입력/출력회로 및 프로그램 가능한 논리소자 Download PDFInfo
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- KR900005702A KR900005702A KR1019890013054A KR890013054A KR900005702A KR 900005702 A KR900005702 A KR 900005702A KR 1019890013054 A KR1019890013054 A KR 1019890013054A KR 890013054 A KR890013054 A KR 890013054A KR 900005702 A KR900005702 A KR 900005702A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/17744—Structural details of routing resources for input/output signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/01759—Coupling arrangements; Interface arrangements with a bidirectional operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17792—Structural details for adapting physical parameters for operating speed
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- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Logic Circuits (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는, 본 발명에 의한 프로그램 가능한 입력/출력회로의 제 1 의 바람직한 실시예의 구성을 나타내는 회로도.
제 2 도는, 본 발명에 의한 프로그램 가능한 입력/출력회로와 결합되는 프로그램 가능한 논리소자(PLD)의 비교예의 구성을 나타내는 블록도.
제 3 도는, 본 발명에 의한 PLD의 바람직한 실시예의 구성을 나타내는 블록도.
제 4 도는, 본 발명에 의한 프로그램 가능한 입력/출력회로의 제 2 의 바람직한 실시예의 구성을 나타내는 회로도.
Claims (9)
- 집적회로의 외부회로와 내부 논리회로 사이의 인터페이스를 행하기 위하여 프로그램 가능한 집적회로 내에서 사용되는 프로그램 가능한 입력/출력회로로서 ; 내부 논리회로의 버스에 접속되는 입력/출력단자(40)와 ; 내부 논리회로의 프로그램 가능한 배선에 접속되는 입력단자(42)와 ; 회로의 외부에서 공급되는 입력신호를 상기 입력/출력단자(40) 및 상기 입력단자(42)중의 어느 하나로 전달하기 위한 3상태 입력 버퍼(44),(48) 및 ; 내부 논리회로에서 상기 입력/출력단자(40)로 공급되는 출력신호를 회로의 외부로 전달하기 위한 3상태 출력버퍼(24)로 구성되는 프로그램 가능한 입력/출력회로.
- 제 1 항에 있어서, 상기 입력신호는 TTL 또는 CMOS 논리레벨에서 내부 논리레벨로 변환하기 위한 입력버퍼(18)를 더욱 포함하는 프로그램 가능한 입력/출력회로.
- 제 1 항에 있어서, 상기 3상태 입력버퍼(44),(48)는, 상기 입력신호를 상기 입력/출력단자(40)로 전달하기 위한 제 1 의 3상태 출력버퍼(44)와, 상기 입력신호를 상기 입력단자(42)로 전달하기 위하여 메모리셀(M)내에 기억된 내용에 따라서 스위치 온 및 스위치 오프되는 제 2 의 3상태 입력버퍼(48)를 포함하는 프로그램 가능한 입력/출력회로.
- 제 3 항에 있어서, 그의 내부에 메모리셀(M)을 포함하여, 상기 제 1 의 3상태 입력버퍼(44)에 대한 상태 제어신호로서 상기 입력단자(42)를 통하여 들어온 어스 신호 및 칩 인에이블 신호(CE) 중의 어느 하나를 선택하는 2입력 멀티플렉서(50)를 더욱 포함하는 프로그램 가능한 입력/출력회로.
- 제 1 항에 있어서, 상기 출력버퍼(24)의 온/오프 상태는 내부 논리회로로부터 출력제어단자(26)로 인가되는 출력 인에이블 신호에 의하여 제어되는 프로그램 가능한 입력/출력회로.
- 제 1 항에 있어서, 상기 입력신호가 인가되는 패드(16)의 전위를 끌어올리기 위한 풀업저항(51)과, 상기 풀업저항(51)의 스위치 온 및 스위치 오프를 위한 메모리셀(M)을 그의 내부에 내장하는 패스 트랜지스터(52)를 더욱 포함하는 프로그램 가능한 입력/출력회로.
- 제 1 항에 있어서, 여러 가지 신호를 래치하기 위한 D플립플롭(20)과, 상기 D플립플롭(20)으로부터의 출력 신호 및 통상의 신호중의 어느 하나를 선택하기 위한 2입력 멀티플렉서(22)를 더욱 포함하는 프로그램 가능한 입력/출력회로.
- 제 1 항에 있어서, 리셋트 신호를 수납하기 위한 제 1 리셋트 단자(70)와, 글로벌 리셋트 신호를 수납하기 위한 제 2 리셋트 단자(72) 및, 상기 제 1 리셋트 단자(70) 및 제 2 리셋트 단자(72)로 인가되는 신호의 논리합의 부정을 리셋트 신호로서 출력하기 위한 NOR 게이트(74)를 더욱 포함하는 프로그램 가능한 입력/출력회로.
- 프로그램 가능한 입력/출력회로 블록(80)을 포함하는 프로그램 가능한 논리소자로서 : 상기 입력/출력회로 블록(80)내에 마련되는 입력/출력제어단자(108),(110)와 ; 전기적 접속 프로그래밍이 가능한 배선 수단(102)과 ; 인에이블 제어 입력단자를 포함하는 3상태 버퍼(106)를 포함하여 구성되며, 상기 3상태 버퍼(106)의 인에이블 제어는 상기 입력/출력회로 블록(80)내에서 발생되는 제어신호에 의하여 수행되는 프로그램 가능한 논리소자.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP225276 | 1988-09-08 | ||
JP22527688 | 1988-09-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900005702A true KR900005702A (ko) | 1990-04-14 |
KR930009153B1 KR930009153B1 (ko) | 1993-09-23 |
Family
ID=16826791
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890013054A KR930009153B1 (ko) | 1988-09-08 | 1989-09-08 | 프로그램 가능한 입력/출력회로 및 프로그램 가능한 논리소자 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4987319A (ko) |
EP (1) | EP0358501A3 (ko) |
KR (1) | KR930009153B1 (ko) |
CA (1) | CA1326716C (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100690992B1 (ko) * | 2000-07-18 | 2007-03-08 | 주식회사 하이닉스반도체 | 데이터 입/출력 버퍼 회로 |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5212652A (en) * | 1989-08-15 | 1993-05-18 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure |
US5644496A (en) * | 1989-08-15 | 1997-07-01 | Advanced Micro Devices, Inc. | Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses |
US5175859A (en) * | 1990-05-01 | 1992-12-29 | Integrated Device Technology, Inc. | Apparatus for disabling unused cache tag input/output pins during processor reset by sensing pull-down resistors connected to disabled pins |
US5017813A (en) * | 1990-05-11 | 1991-05-21 | Actel Corporation | Input/output module with latches |
JPH04192350A (ja) * | 1990-11-24 | 1992-07-10 | Nec Corp | 半導体集積回路装置 |
DE69230510T2 (de) * | 1991-03-28 | 2000-09-14 | Hughes Electronics Corp | Bidirektionaler und programmierbarer E/A-Treiber |
JPH0535668A (ja) * | 1991-07-30 | 1993-02-12 | Toshiba Corp | 信号処理装置 |
US5260611A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic array having local and long distance conductors |
US6759870B2 (en) | 1991-09-03 | 2004-07-06 | Altera Corporation | Programmable logic array integrated circuits |
JPH05181982A (ja) * | 1991-12-27 | 1993-07-23 | Nec Eng Ltd | 大規模集積回路装置 |
US5418911A (en) * | 1992-06-09 | 1995-05-23 | Intel Corporation | Data path switch method and apparatus that provides capacitive load isolation |
JPH0667772A (ja) * | 1992-08-14 | 1994-03-11 | Ricoh Co Ltd | データ伝送装置 |
US5519355A (en) * | 1992-11-19 | 1996-05-21 | At&T Global Information Solutions Company | High speed boundary scan multiplexer |
US5553306A (en) * | 1992-12-29 | 1996-09-03 | International Business Machines Corporation | Method and apparatus for controlling parallel port drivers in a data processing system |
US6130550A (en) * | 1993-01-08 | 2000-10-10 | Dynalogic | Scaleable padframe interface circuit for FPGA yielding improved routability and faster chip layout |
US6002268A (en) * | 1993-01-08 | 1999-12-14 | Dynachip Corporation | FPGA with conductors segmented by active repeaters |
US5424589A (en) * | 1993-02-12 | 1995-06-13 | The Board Of Trustees Of The Leland Stanford Junior University | Electrically programmable inter-chip interconnect architecture |
US5317210A (en) * | 1993-02-23 | 1994-05-31 | Altera Corporation | I/O cell for programmable logic device providing latched, unlatched, and fast inputs |
US5329181A (en) * | 1993-03-05 | 1994-07-12 | Xilinx, Inc. | Complementary macrocell feedback circuit |
US5414380A (en) * | 1993-04-19 | 1995-05-09 | Motorola, Inc. | Integrated circuit with an active-level configurable and method therefor |
KR960008140B1 (ko) * | 1993-12-23 | 1996-06-20 | 현대전자산업 주식회사 | 버스 인터페이스 논리 집적 회로 |
US5742179A (en) * | 1994-01-27 | 1998-04-21 | Dyna Logic Corporation | High speed programmable logic architecture |
US5504440A (en) * | 1994-01-27 | 1996-04-02 | Dyna Logic Corporation | High speed programmable logic architecture |
US5614844A (en) * | 1994-01-27 | 1997-03-25 | Dyna Logic Corporation | High speed programmable logic architecture |
US5432465A (en) * | 1994-05-06 | 1995-07-11 | Windbond Electronics Corp. | Integrated circuit switchable between a line driver function and a bidirectional transceiver function during the packaging stage of the integrated circuit |
JPH08202645A (ja) * | 1995-01-30 | 1996-08-09 | Mazda Motor Corp | 入出力回路構造 |
US5517135A (en) * | 1995-07-26 | 1996-05-14 | Xilinx, Inc. | Bidirectional tristate buffer with default input |
US5970255A (en) | 1995-10-16 | 1999-10-19 | Altera Corporation | System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly |
US5583452A (en) * | 1995-10-26 | 1996-12-10 | Xilinx, Inc. | Tri-directional buffer |
US5677914A (en) * | 1996-04-25 | 1997-10-14 | Hughes Electronics | Test vectro feed-thru |
US5767701A (en) * | 1996-06-28 | 1998-06-16 | Cypress Semiconductor Corp. | Synchronous contention prevention logic for bi-directional signals |
US5789944A (en) * | 1996-06-28 | 1998-08-04 | Cypress Semiconductor Corp. | Asynchronous anticontention logic for bi-directional signals |
US5715197A (en) | 1996-07-29 | 1998-02-03 | Xilinx, Inc. | Multiport RAM with programmable data port configuration |
US5959466A (en) | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
US6150837A (en) | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
US6150840A (en) * | 1997-04-09 | 2000-11-21 | Altera Corporation | Programmable reticle stitching |
IES980711A2 (en) * | 1997-12-15 | 1999-06-30 | Tellabs Res Ltd | Clocking in electronic circuits |
US6177808B1 (en) * | 1998-04-30 | 2001-01-23 | Compaq Computer Corporation | Integration of bidirectional switches with programmable logic |
KR100301809B1 (ko) * | 1998-11-24 | 2001-09-06 | 김영환 | 데이터 입출력 버퍼 제어회로_ |
US6242943B1 (en) * | 1998-12-31 | 2001-06-05 | Khaled Ahmad El-Ayat | Programmable multi-standard I/O architecture for FPGAS |
US6762621B1 (en) | 1998-12-31 | 2004-07-13 | Actel Corporation | Programmable multi-standard I/O architecture for FPGAs |
US6222413B1 (en) * | 1999-03-16 | 2001-04-24 | International Business Machines Corporation | Receiver assisted net driver circuit |
US6271679B1 (en) * | 1999-03-24 | 2001-08-07 | Altera Corporation | I/O cell configuration for multiple I/O standards |
US6836151B1 (en) * | 1999-03-24 | 2004-12-28 | Altera Corporation | I/O cell configuration for multiple I/O standards |
US6590418B1 (en) * | 2001-12-19 | 2003-07-08 | Intel Corporation | Method and apparatus for a programmable output interface |
US7355384B2 (en) * | 2004-04-08 | 2008-04-08 | International Business Machines Corporation | Apparatus, method, and computer program product for monitoring and controlling a microcomputer using a single existing pin |
WO2007124048A2 (en) | 2006-04-19 | 2007-11-01 | Trustees Of Princeton University | A hybrid nanotube/cmos dynamically reconfigurable architecture and an integrated design optimization method and system therefor |
US7859294B1 (en) * | 2009-01-22 | 2010-12-28 | Xilinx, Inc. | Method and arrangement for reducing power in bidirectional input/output ports |
KR101215973B1 (ko) * | 2010-12-30 | 2012-12-27 | 에스케이하이닉스 주식회사 | 집적회로, 집적회로를 포함하는 시스템, 메모리 및 메모리시스템 |
CN104242901A (zh) * | 2013-11-19 | 2014-12-24 | 深圳市邦彦信息技术有限公司 | 单io口同时实现输入输出功能的装置及其实现方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6041364B2 (ja) * | 1980-08-29 | 1985-09-17 | 富士通株式会社 | 出力バッファ回路 |
JPS60252979A (ja) * | 1984-05-30 | 1985-12-13 | Oki Electric Ind Co Ltd | Cmos入出力回路 |
US4695740A (en) * | 1984-09-26 | 1987-09-22 | Xilinx, Inc. | Bidirectional buffer amplifier |
US4763020B1 (en) * | 1985-09-06 | 1997-07-08 | Ricoh Kk | Programmable logic device having plural programmable function cells |
US4876640A (en) * | 1986-02-07 | 1989-10-24 | Advanced Micro Devices, Inc. | Logic controller having programmable logic "and" array using a programmable gray-code counter |
JP2605687B2 (ja) * | 1986-04-17 | 1997-04-30 | 三菱電機株式会社 | 半導体装置 |
US4789951A (en) * | 1986-05-16 | 1988-12-06 | Advanced Micro Devices, Inc. | Programmable array logic cell |
US4774422A (en) * | 1987-05-01 | 1988-09-27 | Digital Equipment Corporation | High speed low pin count bus interface |
US4879481A (en) * | 1988-09-02 | 1989-11-07 | Cypress Semiconductor Corporation | Dual I/O macrocell for high speed synchronous state machine |
US4894563A (en) * | 1988-10-11 | 1990-01-16 | Atmel Corporation | Output macrocell for programmable logic device |
US4912345A (en) * | 1988-12-29 | 1990-03-27 | Sgs-Thomson Microelectronics, Inc. | Programmable summing functions for programmable logic devices |
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1989
- 1989-09-06 US US07/403,443 patent/US4987319A/en not_active Expired - Lifetime
- 1989-09-07 CA CA000610655A patent/CA1326716C/en not_active Expired - Fee Related
- 1989-09-07 EP EP19890309066 patent/EP0358501A3/en not_active Ceased
- 1989-09-08 KR KR1019890013054A patent/KR930009153B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100690992B1 (ko) * | 2000-07-18 | 2007-03-08 | 주식회사 하이닉스반도체 | 데이터 입/출력 버퍼 회로 |
Also Published As
Publication number | Publication date |
---|---|
EP0358501A3 (en) | 1990-09-05 |
EP0358501A2 (en) | 1990-03-14 |
US4987319A (en) | 1991-01-22 |
KR930009153B1 (ko) | 1993-09-23 |
CA1326716C (en) | 1994-02-01 |
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