IES980711A2

IES980711A2 - Clocking in electronic circuits

Info

Publication number: IES980711A2
Application number: IE980711A
Authority: IE
Inventors: Kevin Dewar
Original assignee: Tellabs Res Ltd
Priority date: 1997-12-15
Filing date: 1998-08-31
Publication date: 1999-06-30
Also published as: IES80917B2; AU1680399A; IE981055A1; WO1999031803A1

Abstract

A UTOPIA interface (1) for an ATM cell processor ASIC has an on-chip internal clock (10). The clock (10) is connected to a pad (11) which is also connected to an external clock line (3), to a UTOPIA logic block (12), and to a configuration control circuit (13). The pad (11) may be configured as an output so that the clock source is internal, or as an input so that the clock source is external.

Description

•‘Clocking in Electronic Circuits The invention relates to provision of a clock signal for transfer of data between electronic circuits such as ASICs.

One of the problems which faces circuit designers is a lack of flexibility in the available ί clock sources. The clock source may be on one or other of the two interfacing devices, or it may be external to them. Another problem is synchronising clock signals between devices if frequency is changed.

The invention is directed towards providing a clock circuit to provide additional flexibility in provision of clock signals for interfacing of devices such as ASICs.

Another object is to improve synchronisation of data between interfacing devices.

According to the invention, there is provided a circuit interface comprising a terminal for conducting an external clock signal and a terminal for conducting an internal clock signal, the terminals being interconnected. This arrangement is hereinafter referred to as a “star pad. Because the terminals are interconnected there is always synchronisation of internal and external clocking. For example, if the external clock signal is skewed due to high capacitive loading externally of the chip there will be the same effect both internally and externally.

Preferably, the star pad is connected to an internal clock source. This allows the star pad to act as a clock output with excellent intemal/extemal synchronisation.

In one embodiment, the star pad is bi-directional and further comprises means for switching between the internal clock and an external clock. This allows excellent IE 980710 -2The switching means may comprise a tri-state buffer and means for delivering configuration control signals.

The configuration control means may comprise a circuit register. As little as one bit may be used for configuration control of a tri-state buffer. This allows control to be achieved in a very simple manner with little circuit overhead.

I The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which:Fig. I is a schematic representation of part of a circuit interface of the invention; and Fig. 2 is a diagram showing a star pad of the interface in more detail.

Referring to the drawing there is illustrated a UTOPIA interface for an ATM cell processing ASIC device. The interface is indicated by the numeral l and the chip boundary by the numeral 2. An external clock signal line 3, an output data bus 4, and an input data bus 5 cross the chip boundary 2.

The interface l comprises an on-chip internal clock 10. The internal clock 10 is connected to a pad 11. which is also connected to the external clock line 3, to a UTOPIA logic block 12, and to a configuration control circuit 13.

The configuration control circuit 13 is an ASIC register having a single bit dedicated to provide a configuration control signal to the star pad circuit 11.

The pad 11 itself is shown more clearly in Fig. 2. It has a terminal 14 for connection to the external clock line 3. and is connected internally by lines 15 and 16 to the internal clock source 10 and the UTOPIA logic block 12 respectively . Switching is performed by IE 980711 -3 a tri-state buffer l 7, which is connected to the configuration control circuit 13. Because of the star interconnection arrangement, the pad 11 is hereinafter referred to as a “star pad”.

For tri-state buffer control, a bit 1 enable signal (“en”) causes configuration as an output. In this case, an internal clock signal “a” drives onto the external clock line 3 via the tristate buffer 17. The signal “q” on the line 16 is logically equal to “a”, and so the UTOPIA logic block takes its clock signal from the internal source 10. A bit 0 disables the tri-state buffer 17 so that “q” is logically equal to the external clock signal. Such a signal may, for example, be provided by a communicating device.

Thus, the star pad 11 allows:configuration as an output, whereby the clock source is internal; or configuration as an input, in which case the clock source is external.

It will be noted that when it is configured as an output, the star pad 11 ensures that there is a proper timing relationship between the external clock and output data signals i.e. there is always some positive hold-time on the data. This is because the star pad 11 is used as a star-point before the timing. The star pad also allows self-compensation for the actual loading on the clock and data pads. For example, clock skewing due to high capacative loading externally of the chip has the same effect both internally and externally.

Because the state of the star pad 11 is controlled by the configuration control sub-circuit 13, there is a great deal of flexibility as the state may be easily changed. The logic block 12 performs the interfacing operation in conjunction w ith the relevant clock signals.

The invention is not limited to the embodiments described, but may be varied in construction and detail. For example, the star pad need not include a switching means, in IE 980711 -4which case the advantage of excellent synchronisation is still achieved. In this example, the clock source may be set permanently as either the internal clock 10 or an external clock. Where a switching means is included, it need not necessarily be a tri-stale buffer.

The invention is not limited to the embodiments described, but may be varied in construction and detail within the scope of the claims.

Claims

1. A circuit interface comprising a terminal for conducting an external clock signal and a terminal for conducting an internal clock signal, the terminals being interconnected to form a star pad. 1

2. A circuit interface as claimed in claim 1, wherein the star pad is connected to an internal clock source.

3. A circuit interface as claimed in claim 2, wherein the star pad is bi-directional and further comprises means for switching between the internal clock and an external clock.

4. A circuit interface as claimed in any preceding claim, wherein the switching means comprises a tri-state buffer and means for delivering configuration control signals, and wherein the configuration control means comprises a circuit register.

5. A circuit interface substantially as described with reference to the drawings.