KR900001834B1 - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR900001834B1
KR900001834B1 KR1019860004508A KR860004508A KR900001834B1 KR 900001834 B1 KR900001834 B1 KR 900001834B1 KR 1019860004508 A KR1019860004508 A KR 1019860004508A KR 860004508 A KR860004508 A KR 860004508A KR 900001834 B1 KR900001834 B1 KR 900001834B1
Authority
KR
South Korea
Prior art keywords
film
semiconductor device
layer wiring
forming
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019860004508A
Other languages
English (en)
Korean (ko)
Other versions
KR870000758A (ko
Inventor
야스가즈 마세
마사히로 아베
마사하루 아오야마
Original Assignee
가부시끼가이샤 도오시바
와타리 스기이찌로
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 도오시바, 와타리 스기이찌로 filed Critical 가부시끼가이샤 도오시바
Publication of KR870000758A publication Critical patent/KR870000758A/ko
Application granted granted Critical
Publication of KR900001834B1 publication Critical patent/KR900001834B1/ko
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/097—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by thermally treating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/937—Hillock prevention

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019860004508A 1985-06-06 1986-06-05 반도체장치의 제조방법 Expired KR900001834B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60-123002 1985-06-06
JP60123002A JPS61280638A (ja) 1985-06-06 1985-06-06 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR870000758A KR870000758A (ko) 1987-02-20
KR900001834B1 true KR900001834B1 (ko) 1990-03-24

Family

ID=14849830

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860004508A Expired KR900001834B1 (ko) 1985-06-06 1986-06-05 반도체장치의 제조방법

Country Status (5)

Country Link
US (1) US4728627A (https=)
EP (1) EP0216017B1 (https=)
JP (1) JPS61280638A (https=)
KR (1) KR900001834B1 (https=)
DE (1) DE3684844D1 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194644A (ja) * 1986-02-20 1987-08-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
US4970573A (en) * 1986-07-01 1990-11-13 Harris Corporation Self-planarized gold interconnect layer
TW214599B (https=) * 1990-10-15 1993-10-11 Seiko Epson Corp
NL9100094A (nl) * 1991-01-21 1992-08-17 Koninkl Philips Electronics Nv Halfgeleiderinrichting en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting.
JPH05267471A (ja) * 1991-04-05 1993-10-15 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH0555223A (ja) * 1991-08-27 1993-03-05 Nippon Precision Circuits Kk 集積回路装置の製造方法
KR950006343B1 (ko) * 1992-05-16 1995-06-14 금성일렉트론주식회사 반도체 장치의 제조방법
US5937327A (en) * 1993-04-23 1999-08-10 Ricoh Company, Ltd. Method for improving wiring contact in semiconductor devices
USRE36475E (en) 1993-09-15 1999-12-28 Hyundai Electronics Industries Co., Ltd. Method of forming a via plug in a semiconductor device
KR0140646B1 (ko) * 1994-01-12 1998-07-15 문정환 반도체장치의 제조방법
JPH08130246A (ja) * 1994-10-28 1996-05-21 Ricoh Co Ltd 半導体装置とその製造方法
US5726498A (en) * 1995-05-26 1998-03-10 International Business Machines Corporation Wire shape conferring reduced crosstalk and formation methods
KR100252309B1 (ko) * 1997-03-03 2000-04-15 구본준, 론 위라하디락사 박막 트랜지스터 어레이의 금속 배선 연결 방법및 그 구조
US6594894B1 (en) * 1997-09-30 2003-07-22 The United States Of America As Represented By The Secretary Of The Air Force Planar-processing compatible metallic micro-extrusion process
US6924316B2 (en) * 2001-06-18 2005-08-02 Japan National Oil Corporation Method for producing hydrocarbons by Fischer-Tropsch process
JP6298312B2 (ja) * 2014-02-13 2018-03-20 エイブリック株式会社 半導体装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3132809A1 (de) * 1981-08-19 1983-03-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-feldeffekttransistoren, insbesondere von komplementaeren mos-feldeffekttransistorenschaltungen mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene

Also Published As

Publication number Publication date
KR870000758A (ko) 1987-02-20
JPS61280638A (ja) 1986-12-11
EP0216017B1 (en) 1992-04-15
DE3684844D1 (de) 1992-05-21
US4728627A (en) 1988-03-01
EP0216017A3 (en) 1988-09-21
JPH0418701B2 (https=) 1992-03-27
EP0216017A2 (en) 1987-04-01

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