KR890005869A - 회로기판의 공동에 붙박힌 액티브 디바이스를 갖는 반도체 모듈 - Google Patents

회로기판의 공동에 붙박힌 액티브 디바이스를 갖는 반도체 모듈 Download PDF

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Publication number
KR890005869A
KR890005869A KR1019880011019A KR880011019A KR890005869A KR 890005869 A KR890005869 A KR 890005869A KR 1019880011019 A KR1019880011019 A KR 1019880011019A KR 880011019 A KR880011019 A KR 880011019A KR 890005869 A KR890005869 A KR 890005869A
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South Korea
Prior art keywords
module
cavity
deposited
layer
active device
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KR1019880011019A
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English (en)
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에스·파이 윌리암
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페어차일드 세미컨덕터 코포레이션
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Publication of KR890005869A publication Critical patent/KR890005869A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

내용 없음

Description

회로기판의 공동에 붙박힌 액티브 디바이스를 갖는 반도체 모듈
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본발명의 바람직한 구체예에서의 혼성집적회로 모듈의 횡단면도이다.
제2-3도는 제1도의 디바이스를 만드는 본 발명의 한 구체예에 따르는 단계를 도시한 것이다.

Claims (10)

  1. 공동이 새겨진 몸체와 공동위에 붙박힌 액티부 디바이스로 구성되며 일반적으로 액티브 디바이스의 윗표면이 모체의 윗표면과 함꼐 플라나 구조를 갖는 것으로 이루어진 반도체 모듈.
  2. 제 1항에 있어서, 몸체가 실리콘 회로기판으로 구성된 모듈.
  3. 제 2항에 있어서, 공동의 크기가 실제로 액티브 디바이스의 크기와 동일한 모듈.
  4. 제 3항에 있어서, 몸체가 회로기판위에 침적된 플라나화 층(planarizing layer)및 액티브 디바이스의 윗표면과 함께 플라나 구조를 가지며 액티브 디바이스의 윗표면과 접촉되어 있는 금속층이 플라나화 층위에 침적된 것으로 구성된 모듈.
  5. 여러개의 공동이 새겨진 실리콘 회로기판 ; 회로기판의 윗표면과 각 공동의 내표면위에 연속적으로 침적된 제 1금속층 ; 일반적으로 공동과 맞추어진 구멍을 가지며 제 1금속층위에 침적된 플라나화 층 ; 플라나화 층위에 침적된 패턴을 갖춘 제 2금속층 ; 및 제 2금속층과 함께 윗표면이 플라나 구조를 가지며 금속층과 연결되어 있는 공동에 침적된 액티브 디바이스로 구성된 반도체 모듈.
  6. 제 5항에 있어서, 플라나화층이 유전물질로 만들어진 모듈.
  7. 제 6항에 있어서, 추적 전도체를 만들기 위한 패턴을 갖는 여러개의 제 2금속층이 존재하는 모듈.
  8. 제 7항에 있어서, 유전층이 각각의 제 2금속층 사이에 놓여지는 것으로 더욱 구성되는 모듈.
  9. 제 8항에 있어서, 두개의 제 2금속층 사이에 침적되어 서로 연결시키는 금속 바이어스로 더욱 구성된 모듈.
  10. 제 9항에 있어서, 액티브 디바이스가 집적회로인 모듈.
    ※ 참고사항 : 최초 출원 내용에 의하여 공개하는 것임.
KR1019880011019A 1987-09-11 1988-08-30 회로기판의 공동에 붙박힌 액티브 디바이스를 갖는 반도체 모듈 KR890005869A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9610387A 1987-09-11 1987-09-11
US096,103 1987-09-11

Publications (1)

Publication Number Publication Date
KR890005869A true KR890005869A (ko) 1989-05-17

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KR1019880011019A KR890005869A (ko) 1987-09-11 1988-08-30 회로기판의 공동에 붙박힌 액티브 디바이스를 갖는 반도체 모듈

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EP (1) EP0306890A1 (ko)
JP (1) JPH01157560A (ko)
KR (1) KR890005869A (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5032896A (en) * 1989-08-31 1991-07-16 Hughes Aircraft Company 3-D integrated circuit assembly employing discrete chips
DE4116321A1 (de) * 1991-05-16 1991-11-28 Ermic Gmbh Verfahren zur selektiven haeusung von sensor-halbleiterbauelementen in chip-on -boardtechnik
JPH07211856A (ja) * 1994-01-12 1995-08-11 Fujitsu Ltd 集積回路モジュール

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5293285A (en) * 1976-02-02 1977-08-05 Hitachi Ltd Structure for semiconductor device
JPS6281745A (ja) * 1985-10-05 1987-04-15 Fujitsu Ltd ウエハ−規模のｌｓｉ半導体装置とその製造方法

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EP0306890A1 (en) 1989-03-15

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