KR880012011A - 논리회로 - Google Patents
논리회로 Download PDFInfo
- Publication number
- KR880012011A KR880012011A KR1019880003320A KR880003320A KR880012011A KR 880012011 A KR880012011 A KR 880012011A KR 1019880003320 A KR1019880003320 A KR 1019880003320A KR 880003320 A KR880003320 A KR 880003320A KR 880012011 A KR880012011 A KR 880012011A
- Authority
- KR
- South Korea
- Prior art keywords
- load circuit
- logic circuit
- control
- power supply
- control transistor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
- H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/088—Transistor-transistor logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 논리회로의 구성을 나타낸 회로도.
제2도는 상기 제1실시예의 동작파형도.
제3도는 본 발명이 제2실시예에 따른 논리회로의 구성을 나타낸 회로도.
Claims (4)
- 제1, 제2전원단자(Vcc, 접지)와; 입력 신호를 받아들이는 입력부(I);이 입력부(I)로부터의 신호에 의해 그 도통이 제어되는 제어트랜지스터(Q2)와, 이 제어트랜지스터(Q2)의 일단과 상기 제1전원단자(Vcc)간에 접속되어 그 값이 상기 제어트랜지스터(Q2)의 일단의 전위 혹은 상기 입력부(I)의 출력에 의해 변화되어지는 부하회로를 갖추어 이루어진 제어부(II) 및; 상기 제1, 제2전원단자(Vcc,접지)간에 직렬로 접속되어 상기 제어부(II)로부터의 제어신호에 의해 그 도통이 제어되는 제1, 제2트랜지스터(Q5,Q6)를 갖추어 이루어진 출력부(III)가 구비되어 구성된 것을 특징으로 하는 논리회로.
- 제1항에 있어서, 상기 부하회로는 정저항 소자로 이루어진 제1부하회로(R4)와 가변 저항 소자를 갖춘 제2부하회로로 이루어진 것을 특징으로 하는 논리회로.
- 제2항에 있어서, 상기 제2부하회로는 직렬로 접속된 다이오드 및 저항으로 이루어진 부하회로(1)인 것을 특징으로 하는 논리회로.
- 제2항에 있어서, 상기 제2부하회로는 P채널 FET(P2)인 것을 특징으로 하는 논리회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62071874A JPS63240128A (ja) | 1987-03-27 | 1987-03-27 | 論理回路 |
JP62-71874 | 1987-03-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880012011A true KR880012011A (ko) | 1988-10-31 |
KR910001383B1 KR910001383B1 (ko) | 1991-03-04 |
Family
ID=13473097
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880003320A KR910001383B1 (ko) | 1987-03-27 | 1988-03-26 | 논리회로 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4877975A (ko) |
EP (1) | EP0285068A3 (ko) |
JP (1) | JPS63240128A (ko) |
KR (1) | KR910001383B1 (ko) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2635805B2 (ja) * | 1990-07-31 | 1997-07-30 | 株式会社東芝 | 低ノイズ型出力バッファ回路 |
US5218243A (en) * | 1991-11-20 | 1993-06-08 | National Semiconductor Corporation | Bicmos ttl output buffer circuit with reduced power dissipation |
JP3142018B2 (ja) * | 1992-03-12 | 2001-03-07 | 日本テキサス・インスツルメンツ株式会社 | 負荷駆動回路 |
US5343092A (en) * | 1992-04-27 | 1994-08-30 | International Business Machines Corporation | Self-biased feedback-controlled active pull-down signal switching |
JP3338783B2 (ja) * | 1998-09-24 | 2002-10-28 | エヌイーシーアクセステクニカ株式会社 | トランジスタ回路 |
US9018986B2 (en) * | 2013-01-21 | 2015-04-28 | Via Technologies, Inc. | Output buffers |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5720027A (en) * | 1980-06-25 | 1982-02-02 | Nec Corp | Logical gate circuit |
US4409498A (en) * | 1980-12-30 | 1983-10-11 | International Business Machines Corporation | Transient controlled current switch |
US4605870A (en) * | 1983-03-25 | 1986-08-12 | Ibm Corporation | High speed low power current controlled gate circuit |
US4567378A (en) * | 1984-06-13 | 1986-01-28 | International Business Machines Corporation | Driver circuit for controlling signal rise and fall in field effect transistor processors |
US4737665A (en) * | 1985-01-15 | 1988-04-12 | Texas Instruments Incorporated | Adjustable speed up circuit for TTL-type gates |
JPH0720060B2 (ja) * | 1985-08-14 | 1995-03-06 | 株式会社東芝 | 出力回路装置 |
US4622482A (en) * | 1985-08-30 | 1986-11-11 | Motorola, Inc. | Slew rate limited driver circuit which minimizes crossover distortion |
US4746817A (en) * | 1987-03-16 | 1988-05-24 | International Business Machines Corporation | BIFET logic circuit |
-
1987
- 1987-03-27 JP JP62071874A patent/JPS63240128A/ja active Granted
-
1988
- 1988-03-25 US US07/173,668 patent/US4877975A/en not_active Expired - Lifetime
- 1988-03-26 KR KR1019880003320A patent/KR910001383B1/ko not_active IP Right Cessation
- 1988-03-28 EP EP88104986A patent/EP0285068A3/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
US4877975A (en) | 1989-10-31 |
JPH0519328B2 (ko) | 1993-03-16 |
EP0285068A3 (en) | 1990-06-13 |
JPS63240128A (ja) | 1988-10-05 |
KR910001383B1 (ko) | 1991-03-04 |
EP0285068A2 (en) | 1988-10-05 |
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