KR850004684A - 반도체 기억 장치 - Google Patents
반도체 기억 장치 Download PDFInfo
- Publication number
- KR850004684A KR850004684A KR1019840007504A KR840007504A KR850004684A KR 850004684 A KR850004684 A KR 850004684A KR 1019840007504 A KR1019840007504 A KR 1019840007504A KR 840007504 A KR840007504 A KR 840007504A KR 850004684 A KR850004684 A KR 850004684A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor memory
- memory
- circuits
- coupled
- memory array
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims 6
- 239000011159 matrix material Substances 0.000 claims 1
- 230000001052 transient effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000000872 buffer Substances 0.000 description 2
- 101000773153 Homo sapiens Thioredoxin-like protein 4A Proteins 0.000 description 1
- 102100030272 Thioredoxin-like protein 4A Human genes 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 1실시예를 도시한 회로도.
제3도는 그 데이터 출력 버퍼와 데이터 입력 버퍼 DIB1 내지 DIB4 및 타이밍 발생회로 TG의 일부의 1실시예를 도시한 불록 도면.
제4도는 제3도의 회로 불록 R1 및 W1의 구체적인 회로도.
Claims (5)
- 다음 사항으로 되는 반도체 메모리 메모리 어레이, 상기 메모리 어레이에 결합 되어야할 다수개의 호출회로, 컬럼 어드레스 스트로우브 신호의 과도 변화를 검출하는 것에 의해서 타이밍 신호를 형성하는 타이밍 발생회로, 그리고, 상기 타이밍 신호를 받는 것에 의해서, 상기 다수개의 호출 회로를 차례로 동작시키는 제어 신호를 출력하는 제어 회로로 된다.
- 특허 청구의 범위 제1항의 반도체 메모리에 있어서, 상기 제어 회로는, 상기 타이밍 신호를 쉬프트 펄스로서 받는 쉬프트 레지스터로 된다.
- 특허 청구의 범위 제1항의 반도체 메모리에 있어서, 상기 메모리 어레이는, 매트릭스로 배치된 다수개의 다이나믹형 메모리 셀, 각 다이나믹형 메모리 셀의 선택 단자에 결합된 다수개의 데이터선, 그리고 각 다이나믹형 메모리 셀의 데이터 입출력 단자에 결합된 다수개의 데이터선으로 된다.
- 특허 청구의 범위 제3항의 반도체 메모리에 있어서, 상기 다수개의 호출 회로의 출력 단자는, 서로가 공통으로 접속 되어 있다.
- 특허 청구의 범위 제4항에 있어서 반도체 메모리는 또, 상기 메모리 어레이에 결합되어야할 다수 개의 기억 회로로 되고, 상기 기억 회로는, 상기 쉬프트 레지스터에서 출력되는 제어 신호에 의해서 차례로 동작 된다.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58-241966 | 1983-12-23 | ||
JP58241966A JPS60136086A (ja) | 1983-12-23 | 1983-12-23 | 半導体記憶装置 |
JP83-241966 | 1983-12-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR850004684A true KR850004684A (ko) | 1985-07-25 |
KR920010560B1 KR920010560B1 (ko) | 1992-12-05 |
Family
ID=17082224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019840007504A KR920010560B1 (ko) | 1983-12-23 | 1984-11-29 | 반도체 기억장치 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4875192A (ko) |
JP (1) | JPS60136086A (ko) |
KR (1) | KR920010560B1 (ko) |
GB (1) | GB2152777A (ko) |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61110399A (ja) * | 1984-11-05 | 1986-05-28 | Toshiba Corp | ダイナミツクメモリのデ−タ出力回路 |
JPS6240693A (ja) * | 1985-08-16 | 1987-02-21 | Fujitsu Ltd | ニブル・モ−ド機能を有する半導体記憶装置 |
JPS63257193A (ja) * | 1987-04-13 | 1988-10-25 | 日本特殊陶業株式会社 | 点火プラグ |
JP2569554B2 (ja) * | 1987-05-13 | 1997-01-08 | 三菱電機株式会社 | ダイナミツクram |
US4951246A (en) * | 1989-08-08 | 1990-08-21 | Cray Research, Inc. | Nibble-mode dram solid state storage device |
IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
US6751696B2 (en) | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |
US5291450A (en) * | 1990-11-28 | 1994-03-01 | Matsushita Electric Industrial Co., Ltd. | Read circuit of dynamic random access memory |
DE4114744C1 (ko) * | 1991-05-06 | 1992-05-27 | Siemens Ag, 8000 Muenchen, De | |
US6804760B2 (en) | 1994-12-23 | 2004-10-12 | Micron Technology, Inc. | Method for determining a type of memory present in a system |
US5682354A (en) * | 1995-11-06 | 1997-10-28 | Micron Technology, Inc. | CAS recognition in burst extended data out DRAM |
US5526320A (en) | 1994-12-23 | 1996-06-11 | Micron Technology Inc. | Burst EDO memory device |
US6525971B2 (en) | 1995-06-30 | 2003-02-25 | Micron Technology, Inc. | Distributed write data drivers for burst access memories |
US5675549A (en) * | 1994-12-23 | 1997-10-07 | Micron Technology, Inc. | Burst EDO memory device address counter |
US5652724A (en) * | 1994-12-23 | 1997-07-29 | Micron Technology, Inc. | Burst EDO memory device having pipelined output buffer |
US5610864A (en) * | 1994-12-23 | 1997-03-11 | Micron Technology, Inc. | Burst EDO memory device with maximized write cycle timing |
US5729503A (en) * | 1994-12-23 | 1998-03-17 | Micron Technology, Inc. | Address transition detection on a synchronous design |
US5721859A (en) * | 1994-12-23 | 1998-02-24 | Micron Technology, Inc. | Counter control circuit in a burst memory |
US5598376A (en) * | 1994-12-23 | 1997-01-28 | Micron Technology, Inc. | Distributed write data drivers for burst access memories |
US5668773A (en) * | 1994-12-23 | 1997-09-16 | Micron Technology, Inc. | Synchronous burst extended data out DRAM |
US5640364A (en) * | 1994-12-23 | 1997-06-17 | Micron Technology, Inc. | Self-enabling pulse trapping circuit |
US5717654A (en) * | 1995-02-10 | 1998-02-10 | Micron Technology, Inc. | Burst EDO memory device with maximized write cycle timing |
US5850368A (en) * | 1995-06-01 | 1998-12-15 | Micron Technology, Inc. | Burst EDO memory address counter |
US6810449B1 (en) | 1995-10-19 | 2004-10-26 | Rambus, Inc. | Protocol for communication with dynamic memory |
US6470405B2 (en) | 1995-10-19 | 2002-10-22 | Rambus Inc. | Protocol for communication with dynamic memory |
US5729504A (en) * | 1995-12-14 | 1998-03-17 | Micron Technology, Inc. | Continuous burst edo memory device |
US7681005B1 (en) | 1996-01-11 | 2010-03-16 | Micron Technology, Inc. | Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation |
US5966724A (en) * | 1996-01-11 | 1999-10-12 | Micron Technology, Inc. | Synchronous memory device with dual page and burst mode operations |
US6209071B1 (en) | 1996-05-07 | 2001-03-27 | Rambus Inc. | Asynchronous request/synchronous data dynamic random access memory |
US6981126B1 (en) | 1996-07-03 | 2005-12-27 | Micron Technology, Inc. | Continuous interleave burst access |
US6401186B1 (en) | 1996-07-03 | 2002-06-04 | Micron Technology, Inc. | Continuous burst memory which anticipates a next requested start address |
US6266379B1 (en) | 1997-06-20 | 2001-07-24 | Massachusetts Institute Of Technology | Digital transmitter with equalization |
US6401167B1 (en) | 1997-10-10 | 2002-06-04 | Rambus Incorporated | High performance cost optimized memory |
US6343352B1 (en) | 1997-10-10 | 2002-01-29 | Rambus Inc. | Method and apparatus for two step memory write operations |
WO1999019874A1 (en) | 1997-10-10 | 1999-04-22 | Rambus Incorporated | Power control system for synchronous memory device |
US7103742B1 (en) | 1997-12-03 | 2006-09-05 | Micron Technology, Inc. | Burst/pipelined edo memory device |
DE19822750A1 (de) * | 1998-05-20 | 1999-11-25 | Siemens Ag | Halbleiterspeicher mit differentiellen Bitleitungen |
US6675272B2 (en) | 2001-04-24 | 2004-01-06 | Rambus Inc. | Method and apparatus for coordinating memory operations among diversely-located memory components |
US7301831B2 (en) | 2004-09-15 | 2007-11-27 | Rambus Inc. | Memory systems with variable delays for write data signals |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
KR101666590B1 (ko) * | 2009-02-23 | 2016-10-14 | 삼성전자 주식회사 | 글리치 프리 및 파워 세이빙 기능을 갖는 시프트 레지스터 회로 |
KR20200106733A (ko) * | 2019-03-05 | 2020-09-15 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6057156B2 (ja) * | 1978-05-24 | 1985-12-13 | 株式会社日立製作所 | 半導体メモリ装置 |
JPS5951073B2 (ja) * | 1980-03-27 | 1984-12-12 | 富士通株式会社 | 半導体記憶装置 |
JPS5727477A (en) * | 1980-07-23 | 1982-02-13 | Nec Corp | Memory circuit |
US4344156A (en) * | 1980-10-10 | 1982-08-10 | Inmos Corporation | High speed data transfer for a semiconductor memory |
US4338679A (en) * | 1980-12-24 | 1982-07-06 | Mostek Corporation | Row driver circuit for semiconductor memory |
US4405996A (en) * | 1981-02-06 | 1983-09-20 | Rca Corporation | Precharge with power conservation |
JPS57186289A (en) * | 1981-05-13 | 1982-11-16 | Hitachi Ltd | Semiconductor memory |
JPS6042547B2 (ja) * | 1981-10-08 | 1985-09-24 | 三菱電機株式会社 | 半導体記憶装置 |
JPS58220294A (ja) * | 1982-06-16 | 1983-12-21 | Mitsubishi Electric Corp | 半導体記憶装置 |
DE3243496A1 (de) * | 1982-11-24 | 1984-05-24 | Siemens AG, 1000 Berlin und 8000 München | Integrierte halbleiterschaltung mit einem dynamischen schreib-lese-speicher |
US4567579A (en) * | 1983-07-08 | 1986-01-28 | Texas Instruments Incorporated | Dynamic memory with high speed nibble mode |
JPS60117492A (ja) * | 1983-11-29 | 1985-06-24 | Fujitsu Ltd | 半導体記憶装置 |
-
1983
- 1983-12-23 JP JP58241966A patent/JPS60136086A/ja active Granted
-
1984
- 1984-11-29 KR KR1019840007504A patent/KR920010560B1/ko not_active IP Right Cessation
- 1984-12-17 GB GB08431762A patent/GB2152777A/en not_active Withdrawn
-
1987
- 1987-11-30 US US07/127,621 patent/US4875192A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB8431762D0 (en) | 1985-01-30 |
US4875192A (en) | 1989-10-17 |
GB2152777A (en) | 1985-08-07 |
KR920010560B1 (ko) | 1992-12-05 |
JPH0546040B2 (ko) | 1993-07-12 |
JPS60136086A (ja) | 1985-07-19 |
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