KR20210034873A - 메모리 장치 및 그 동작 방법 - Google Patents

메모리 장치 및 그 동작 방법 Download PDF

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Publication number
KR20210034873A
KR20210034873A KR1020190116755A KR20190116755A KR20210034873A KR 20210034873 A KR20210034873 A KR 20210034873A KR 1020190116755 A KR1020190116755 A KR 1020190116755A KR 20190116755 A KR20190116755 A KR 20190116755A KR 20210034873 A KR20210034873 A KR 20210034873A
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KR
South Korea
Prior art keywords
buffer
data
latch
bit line
cache
Prior art date
Application number
KR1020190116755A
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English (en)
Korean (ko)
Inventor
양철우
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020190116755A priority Critical patent/KR20210034873A/ko
Priority to US16/853,337 priority patent/US11049535B2/en
Priority to CN202010547078.0A priority patent/CN112542186B/zh
Publication of KR20210034873A publication Critical patent/KR20210034873A/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
KR1020190116755A 2019-09-23 2019-09-23 메모리 장치 및 그 동작 방법 KR20210034873A (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020190116755A KR20210034873A (ko) 2019-09-23 2019-09-23 메모리 장치 및 그 동작 방법
US16/853,337 US11049535B2 (en) 2019-09-23 2020-04-20 Memory device and method of operating the memory device
CN202010547078.0A CN112542186B (zh) 2019-09-23 2020-06-16 存储器设备和操作存储器设备的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190116755A KR20210034873A (ko) 2019-09-23 2019-09-23 메모리 장치 및 그 동작 방법

Publications (1)

Publication Number Publication Date
KR20210034873A true KR20210034873A (ko) 2021-03-31

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020190116755A KR20210034873A (ko) 2019-09-23 2019-09-23 메모리 장치 및 그 동작 방법

Country Status (3)

Country Link
US (1) US11049535B2 (zh)
KR (1) KR20210034873A (zh)
CN (1) CN112542186B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11322213B2 (en) * 2020-06-12 2022-05-03 Sandisk Technologies Llc Enhanced multistate verify techniques in a memory device
KR20210155432A (ko) * 2020-06-15 2021-12-23 삼성전자주식회사 불휘발성 메모리 장치, 및 그것의 동작 방법
CN117116324A (zh) 2021-06-29 2023-11-24 长江存储科技有限责任公司 三维存储器装置中的页缓冲器电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0169419B1 (ko) * 1995-09-28 1999-02-01 김광호 불휘발성 반도체 메모리의 독출방법 및 장치
KR100454119B1 (ko) * 2001-10-24 2004-10-26 삼성전자주식회사 캐쉬 기능을 갖는 불 휘발성 반도체 메모리 장치 및 그것의 프로그램, 읽기, 그리고 페이지 카피백 방법들
KR100672149B1 (ko) * 2005-02-17 2007-01-19 주식회사 하이닉스반도체 불휘발성 메모리 장치의 페이지 버퍼 동작 방법
KR100672150B1 (ko) * 2005-02-23 2007-01-19 주식회사 하이닉스반도체 불휘발성 메모리 장치 및 그것의 페이지 버퍼 동작 방법
US7123521B1 (en) 2005-04-27 2006-10-17 Micron Technology, Inc. Random cache read
KR100739254B1 (ko) * 2006-02-08 2007-07-12 주식회사 하이닉스반도체 프로그램 동작의 패일을 감소시키는 플래시 메모리 장치의페이지 버퍼 회로 및 그 프로그램 동작 방법
US7957197B2 (en) 2008-05-28 2011-06-07 Sandisk Corporation Nonvolatile memory with a current sense amplifier having a precharge circuit and a transfer gate coupled to a sense node
KR101115623B1 (ko) * 2010-07-09 2012-02-15 주식회사 하이닉스반도체 불휘발성 메모리 장치 및 이의 동작 방법
KR102293169B1 (ko) * 2014-06-25 2021-08-26 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 동작 방법
KR102248835B1 (ko) * 2014-09-29 2021-05-10 삼성전자주식회사 불 휘발성 메모리 장치 및 그것의 동작 방법
KR20170069010A (ko) * 2015-12-10 2017-06-20 에스케이하이닉스 주식회사 페이지 버퍼 및 이를 포함하는 메모리 장치

Also Published As

Publication number Publication date
US11049535B2 (en) 2021-06-29
CN112542186A (zh) 2021-03-23
CN112542186B (zh) 2024-01-30
US20210090620A1 (en) 2021-03-25

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