KR20140005107A - 기판, 기판의 제조 방법, 반도체 장치, 및 전자 기기 - Google Patents

기판, 기판의 제조 방법, 반도체 장치, 및 전자 기기 Download PDF

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Publication number
KR20140005107A
KR20140005107A KR1020130077650A KR20130077650A KR20140005107A KR 20140005107 A KR20140005107 A KR 20140005107A KR 1020130077650 A KR1020130077650 A KR 1020130077650A KR 20130077650 A KR20130077650 A KR 20130077650A KR 20140005107 A KR20140005107 A KR 20140005107A
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KR
South Korea
Prior art keywords
insulating layer
hole
base substrate
substrate
layer
Prior art date
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Ceased
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KR1020130077650A
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English (en)
Korean (ko)
Inventor
쯔요시 요다
Original Assignee
세이코 엡슨 가부시키가이샤
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Application filed by 세이코 엡슨 가부시키가이샤 filed Critical 세이코 엡슨 가부시키가이샤
Publication of KR20140005107A publication Critical patent/KR20140005107A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020130077650A 2012-07-04 2013-07-03 기판, 기판의 제조 방법, 반도체 장치, 및 전자 기기 Ceased KR20140005107A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012150345A JP2014013810A (ja) 2012-07-04 2012-07-04 基板、基板の製造方法、半導体装置、及び電子機器
JPJP-P-2012-150345 2012-07-04

Publications (1)

Publication Number Publication Date
KR20140005107A true KR20140005107A (ko) 2014-01-14

Family

ID=49877913

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130077650A Ceased KR20140005107A (ko) 2012-07-04 2013-07-03 기판, 기판의 제조 방법, 반도체 장치, 및 전자 기기

Country Status (5)

Country Link
US (1) US9349673B2 (https=)
JP (1) JP2014013810A (https=)
KR (1) KR20140005107A (https=)
CN (1) CN103531553B (https=)
TW (1) TWI587470B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
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KR20200134264A (ko) * 2019-01-23 2020-12-01 보에 테크놀로지 그룹 컴퍼니 리미티드 디스플레이 기판, 스플라이싱 스크린 및 그의 제조 방법

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SE538062C2 (sv) * 2012-09-27 2016-02-23 Silex Microsystems Ab Kemiskt pläterad metallvia genom kisel
KR102411064B1 (ko) * 2015-03-10 2022-06-21 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그의 제조방법
JP2016225471A (ja) 2015-05-29 2016-12-28 株式会社東芝 半導体装置および半導体装置の製造方法
US10049981B2 (en) * 2016-09-08 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Through via structure, semiconductor device and manufacturing method thereof
JP2018157110A (ja) * 2017-03-17 2018-10-04 東芝メモリ株式会社 半導体装置およびその製造方法
CN110537251B (zh) * 2017-04-25 2023-07-04 三菱电机株式会社 半导体装置
US20190013302A1 (en) * 2017-07-07 2019-01-10 China Wafer Level Csp Co., Ltd. Packaging method and package structure for fingerprint recognition chip and drive chip
US10957712B2 (en) 2017-08-02 2021-03-23 Sharp Kabushiki Kaisha Substrate and method for producing substrate
EP3460835B1 (en) * 2017-09-20 2020-04-01 ams AG Method for manufacturing a semiconductor device and semiconductor device
US10679924B2 (en) 2018-03-05 2020-06-09 Win Semiconductors Corp. Semiconductor device with antenna integrated
KR102933198B1 (ko) * 2020-08-28 2026-03-03 삼성전자주식회사 배선 구조체, 이의 제조 방법 및 배선 구조체를 포함하는 반도체 패키지
US20250234665A1 (en) * 2021-10-26 2025-07-17 Sony Semiconductor Solutions Corporation Semiconductor device, manufacturing method therefor, and electronic apparatus
TWI841118B (zh) * 2022-12-14 2024-05-01 南亞科技股份有限公司 半導體結構及其製造方法

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DE3686721D1 (de) * 1986-10-08 1992-10-15 Ibm Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist.
US5940732A (en) * 1995-11-27 1999-08-17 Semiconductor Energy Laboratory Co., Method of fabricating semiconductor device
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JP4127095B2 (ja) 2003-03-27 2008-07-30 セイコーエプソン株式会社 半導体装置の製造方法
JP2005011920A (ja) * 2003-06-18 2005-01-13 Hitachi Displays Ltd 表示装置とその製造方法
JP4155154B2 (ja) 2003-10-15 2008-09-24 セイコーエプソン株式会社 半導体装置、回路基板、及び電子機器
JP2005235860A (ja) 2004-02-17 2005-09-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
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JP4845368B2 (ja) 2004-10-28 2011-12-28 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
JP4388454B2 (ja) 2004-10-27 2009-12-24 信越半導体株式会社 ワーク保持板並びに半導体ウエーハの製造方法及び研磨方法
JP4501632B2 (ja) 2004-10-27 2010-07-14 セイコーエプソン株式会社 半導体装置の製造方法
JP4873517B2 (ja) 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
JP4694305B2 (ja) 2005-08-16 2011-06-08 ルネサスエレクトロニクス株式会社 半導体ウエハの製造方法
JP5326361B2 (ja) * 2008-05-28 2013-10-30 富士通セミコンダクター株式会社 半導体装置の製造方法
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JP5268618B2 (ja) * 2008-12-18 2013-08-21 株式会社東芝 半導体装置
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JP5423572B2 (ja) 2010-05-07 2014-02-19 セイコーエプソン株式会社 配線基板、圧電発振器、ジャイロセンサー、配線基板の製造方法
KR20110133251A (ko) * 2010-06-04 2011-12-12 삼성전자주식회사 박막 트랜지스터 표시판 및 그 제조 방법

Cited By (2)

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KR20200134264A (ko) * 2019-01-23 2020-12-01 보에 테크놀로지 그룹 컴퍼니 리미티드 디스플레이 기판, 스플라이싱 스크린 및 그의 제조 방법
US11488987B2 (en) 2019-01-23 2022-11-01 Beijing Boe Technology Development Co., Ltd. Display substrate, splicing screen and manufacturing method thereof

Also Published As

Publication number Publication date
TW201403780A (zh) 2014-01-16
CN103531553B (zh) 2018-08-03
US9349673B2 (en) 2016-05-24
US20140008816A1 (en) 2014-01-09
TWI587470B (zh) 2017-06-11
JP2014013810A (ja) 2014-01-23
CN103531553A (zh) 2014-01-22

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