KR20100123766A - Cu 배선막의 형성 방법 - Google Patents
Cu 배선막의 형성 방법 Download PDFInfo
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- KR20100123766A KR20100123766A KR1020107022963A KR20107022963A KR20100123766A KR 20100123766 A KR20100123766 A KR 20100123766A KR 1020107022963 A KR1020107022963 A KR 1020107022963A KR 20107022963 A KR20107022963 A KR 20107022963A KR 20100123766 A KR20100123766 A KR 20100123766A
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- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
- C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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Abstract
Description
도 2 는 종래 기술에 의한 보이드의 발생을 나타내는 SEM 사진 및 그 모식도이다.
도 3 은 종래 기술에 의해 Cu 배선막을 형성한 경우의, 기판의 단면 TEM 사진 및 EDX 분석 결과, 그리고, 테이프 시험 결과를 나타낸 사진이며, 도 3(a-1) 및 도 3(a-2) 는 성막 직후의 경우, 또, 도 3(b-1) 및 도 3(b-2) 는 성막 후 가열 처리한 경우이다.
도 4 는 본 발명에 의해 Cu 배선막을 형성한 경우의, 기판의 단면 TEM 사진 및 테이프 시험 결과를 나타내는 사진이며, 도 4(a-1) 및 도 4(a-2) 는 성막 직후의 경우, 또, 도 4(b-1) 및 도 4(b-2) 는 성막 후 가열 처리한 경우이다.
도 5 는 종래 기술 및 본 발명에 의해 Cu 배선막을 형성한 경우의, 기판 표면의 SEM 사진이며, 도 5(a-1) ∼ 도 5(a-4) 는 종래 기술에 의한 경우, 또, 도 5(b-1) ∼ 도 5(b-4) 는 본 발명에 의한 경우이다.
도 6 은 실시예 1 에 의해 웨이퍼 상에 Cu 배선막을 형성한 경우의 웨이퍼 단면을 나타내는 도면이며, 도 6(a) 는 모식적인 웨이퍼 단면도이고, 도 6(b) 는 그 SEM 사진이다.
102 배리어막
103 PVD-시드막
104 Cu 막
201 기판
202 TiN 배리어막
203 CVD-Cu 막
Claims (7)
- 홀 또는 트렌치가 형성되어 있는 기판 상에 Ti, TiN, Ta, TaN, W, WN, 및 실리사이드에서 선택된 배리어막을 형성한 후, 그 위에 PVD-Co 막을 형성하고, 이 Co 막이 표면에 형성된 홀 또는 트렌치 내를 CVD-Cu 막 또는 PVD-Cu 막으로 매립한 후, 350 ℃ 이하의 온도에서 가열 처리함으로써 Cu 배선막을 형성하는 것을 특징으로 하는 Cu 배선막의 형성 방법.
- 홀 또는 트렌치가 형성되어 있는 기판 상에 Ti, TiN, Ta, TaN, W, WN, 및 실리사이드에서 선택된 배리어막을 형성한 후, 그 위에 PVD-Co 막을 형성하고, 이 Co 막 상에 시드막으로서 CVD-Cu 막 또는 PVD-Cu 막을 형성하고, 이어서 그 시드막이 표면에 형성된 홀 또는 트렌치 내를 도금법에 의해 Cu 막으로 매립한 후, 350 ℃ 이하의 온도에서 가열 처리함으로써 Cu 배선막을 형성하는 것을 특징으로 하는 Cu 배선막의 형성 방법.
- 제 1 항 또는 제 2 항에 있어서,
상기 배리어막이 W 막 또는 TiN 막인 것을 특징으로 하는 Cu 배선막의 형성 방법. - 제 1 항 내지 제 3 항 중 어느 한 항에 있어서,
상기 가열 처리가 250 ∼ 350 ℃ 에서 실시되는 것을 특징으로 하는 Cu 배선막의 형성 방법. - 홀 또는 트렌치가 형성되어 있는 기판 상에 W 배리어막 또는 TiN 배리어막을 형성한 후에 대기 노출시키고, 이어서 TiN 배리어막 상에 PVD-Co 막을 형성한 후에 대기 노출시키거나 또는 대기 노출시키지 않고, 이 Co 막이 표면에 형성된 홀 또는 트렌치 내를 CVD-Cu 막 또는 PVD-Cu 막으로 매립한 후, 350 ℃ 이하의 온도에서 가열 처리함으로써 Cu 배선막을 형성하는 것을 특징으로 하는 Cu 배선막의 형성 방법.
- 홀 또는 트렌치가 형성되어 있는 기판 상에 W 배리어막 또는 TiN 배리어막을 형성한 후에 대기 노출시키고, 이어서 TiN 배리어막 상에 PVD-Co 막을 형성한 후에 대기 노출시키거나 또는 대기 노출시키지 않고, 이 Co 막 상에 시드막으로서 CVD-Cu 막 또는 PVD-Cu 막을 형성하고, 이어서 그 시드막이 표면에 형성된 홀 또는 트렌치 내를 도금법에 의해 Cu 막으로 매립한 후, 350 ℃ 이하의 온도에서 가열 처리함으로써 Cu 배선막을 형성하는 것을 특징으로 하는 Cu 배선막의 형성 방법.
- 제 5 항 또는 제 6 항에 있어서,
상기 가열 처리가 250 ∼ 350 ℃ 에서 실시되는 것을 특징으로 하는 Cu 배선막의 형성 방법.
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JP2008187816 | 2008-07-18 | ||
JPJP-P-2008-187816 | 2008-07-18 |
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KR20100123766A true KR20100123766A (ko) | 2010-11-24 |
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KR1020107022963A Ceased KR20100123766A (ko) | 2008-07-18 | 2009-07-14 | Cu 배선막의 형성 방법 |
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US (1) | US8476161B2 (ko) |
JP (1) | JP5377489B2 (ko) |
KR (1) | KR20100123766A (ko) |
TW (1) | TWI445086B (ko) |
WO (1) | WO2010007991A1 (ko) |
Cited By (1)
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KR20230103893A (ko) * | 2021-12-30 | 2023-07-07 | 주식회사 큐프럼 머티리얼즈 | 루테늄 도금액 조성물 |
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CN104752320B (zh) * | 2013-12-27 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN112885776A (zh) * | 2019-11-29 | 2021-06-01 | 广东汉岂工业技术研发有限公司 | 一种半导体器件及其制程方法 |
CN112201618A (zh) * | 2020-09-30 | 2021-01-08 | 上海华力集成电路制造有限公司 | 一种优化衬垫层质量的方法 |
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US6891269B1 (en) * | 1995-07-05 | 2005-05-10 | Fujitsu Limited | Embedded electroconductive layer structure |
US6399512B1 (en) | 2000-06-15 | 2002-06-04 | Cypress Semiconductor Corporation | Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer |
JP2002110679A (ja) | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP3654354B2 (ja) * | 2001-05-28 | 2005-06-02 | 学校法人早稲田大学 | 超lsi配線板及びその製造方法 |
KR100543458B1 (ko) * | 2003-06-03 | 2006-01-20 | 삼성전자주식회사 | 반도체 장치의 도전성 구조체 형성 방법 |
JP2006093357A (ja) * | 2004-09-22 | 2006-04-06 | Ebara Corp | 半導体装置及びその製造方法、並びに処理液 |
JP2007123853A (ja) | 2005-09-28 | 2007-05-17 | Ebara Corp | 層形成方法、層形成装置、基材処理装置、配線形成方法、および基板の配線構造 |
US20090022891A1 (en) | 2006-02-08 | 2009-01-22 | Jsr Corporation | Method of forming metal film |
US20070210448A1 (en) | 2006-03-10 | 2007-09-13 | International Business Machines Corporation | Electroless cobalt-containing liner for middle-of-the-line (mol) applications |
JP2008098449A (ja) | 2006-10-12 | 2008-04-24 | Ebara Corp | 基板処理装置及び基板処理方法 |
US7704879B2 (en) * | 2007-09-27 | 2010-04-27 | Tokyo Electron Limited | Method of forming low-resistivity recessed features in copper metallization |
US8133555B2 (en) * | 2008-10-14 | 2012-03-13 | Asm Japan K.K. | Method for forming metal film by ALD using beta-diketone metal complex |
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2009
- 2009-07-14 US US12/935,746 patent/US8476161B2/en active Active
- 2009-07-14 WO PCT/JP2009/062745 patent/WO2010007991A1/ja active Application Filing
- 2009-07-14 KR KR1020107022963A patent/KR20100123766A/ko not_active Ceased
- 2009-07-14 JP JP2010520871A patent/JP5377489B2/ja not_active Expired - Fee Related
- 2009-07-16 TW TW098124087A patent/TWI445086B/zh not_active IP Right Cessation
Cited By (1)
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KR20230103893A (ko) * | 2021-12-30 | 2023-07-07 | 주식회사 큐프럼 머티리얼즈 | 루테늄 도금액 조성물 |
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Publication number | Publication date |
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TW201007843A (en) | 2010-02-16 |
US20110104890A1 (en) | 2011-05-05 |
TWI445086B (zh) | 2014-07-11 |
JPWO2010007991A1 (ja) | 2012-01-05 |
US8476161B2 (en) | 2013-07-02 |
WO2010007991A1 (ja) | 2010-01-21 |
JP5377489B2 (ja) | 2013-12-25 |
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