KR20050109501A - 메모리용 가변 리프레시 제어 - Google Patents
메모리용 가변 리프레시 제어 Download PDFInfo
- Publication number
- KR20050109501A KR20050109501A KR1020057015413A KR20057015413A KR20050109501A KR 20050109501 A KR20050109501 A KR 20050109501A KR 1020057015413 A KR1020057015413 A KR 1020057015413A KR 20057015413 A KR20057015413 A KR 20057015413A KR 20050109501 A KR20050109501 A KR 20050109501A
- Authority
- KR
- South Korea
- Prior art keywords
- memory cells
- test
- refresh rate
- test cell
- rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 230000015654 memory Effects 0.000 title claims abstract description 142
- 238000012360 testing method Methods 0.000 claims abstract description 157
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 230000004044 response Effects 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 16
- 238000012544 monitoring process Methods 0.000 claims description 10
- 230000000737 periodic effect Effects 0.000 claims description 3
- 238000013500 data storage Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 101100536515 Arabidopsis thaliana TBL4 gene Proteins 0.000 description 3
- 102100026339 F-box-like/WD repeat-containing protein TBL1X Human genes 0.000 description 3
- 101000835691 Homo sapiens F-box-like/WD repeat-containing protein TBL1X Proteins 0.000 description 3
- 101000835690 Homo sapiens F-box-like/WD repeat-containing protein TBL1Y Proteins 0.000 description 3
- 101100210446 Oryza sativa subsp. japonica XOAT9 gene Proteins 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101001125540 Homo sapiens 26S proteasome regulatory subunit 6A Proteins 0.000 description 1
- 101000891654 Homo sapiens TATA-box-binding protein Proteins 0.000 description 1
- 101000800590 Homo sapiens Transducin beta-like protein 2 Proteins 0.000 description 1
- 101000837456 Homo sapiens Transducin beta-like protein 3 Proteins 0.000 description 1
- 101001026573 Homo sapiens cAMP-dependent protein kinase type I-alpha regulatory subunit Proteins 0.000 description 1
- 102100040296 TATA-box-binding protein Human genes 0.000 description 1
- 102100033248 Transducin beta-like protein 2 Human genes 0.000 description 1
- 102100028683 Transducin beta-like protein 3 Human genes 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 102100037490 cAMP-dependent protein kinase type I-alpha regulatory subunit Human genes 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4061—Calibration or ate or cycle tuning
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/369,985 US6778457B1 (en) | 2003-02-19 | 2003-02-19 | Variable refresh control for a memory |
| US10/369,985 | 2003-02-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20050109501A true KR20050109501A (ko) | 2005-11-21 |
Family
ID=32850368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020057015413A Ceased KR20050109501A (ko) | 2003-02-19 | 2004-02-06 | 메모리용 가변 리프레시 제어 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US6778457B1 (enExample) |
| JP (1) | JP4652324B2 (enExample) |
| KR (1) | KR20050109501A (enExample) |
| CN (1) | CN100587834C (enExample) |
| TW (1) | TWI321321B (enExample) |
| WO (1) | WO2004075256A2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9564207B2 (en) | 2015-02-13 | 2017-02-07 | SK Hynix Inc. | Semiconductor memory device, semiconductor memory system and method for controlling self refresh cycle thereof |
Families Citing this family (86)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8149048B1 (en) | 2000-10-26 | 2012-04-03 | Cypress Semiconductor Corporation | Apparatus and method for programmable power management in a programmable analog circuit block |
| US6724220B1 (en) | 2000-10-26 | 2004-04-20 | Cyress Semiconductor Corporation | Programmable microcontroller architecture (mixed analog/digital) |
| US7765095B1 (en) | 2000-10-26 | 2010-07-27 | Cypress Semiconductor Corporation | Conditional branching in an in-circuit emulation system |
| US8103496B1 (en) | 2000-10-26 | 2012-01-24 | Cypress Semicondutor Corporation | Breakpoint control in an in-circuit emulation system |
| US8176296B2 (en) | 2000-10-26 | 2012-05-08 | Cypress Semiconductor Corporation | Programmable microcontroller architecture |
| US7406674B1 (en) | 2001-10-24 | 2008-07-29 | Cypress Semiconductor Corporation | Method and apparatus for generating microcontroller configuration information |
| US8078970B1 (en) | 2001-11-09 | 2011-12-13 | Cypress Semiconductor Corporation | Graphical user interface with user-selectable list-box |
| US8042093B1 (en) | 2001-11-15 | 2011-10-18 | Cypress Semiconductor Corporation | System providing automatic source code generation for personalization and parameterization of user modules |
| US7770113B1 (en) | 2001-11-19 | 2010-08-03 | Cypress Semiconductor Corporation | System and method for dynamically generating a configuration datasheet |
| US7774190B1 (en) | 2001-11-19 | 2010-08-10 | Cypress Semiconductor Corporation | Sleep and stall in an in-circuit emulation system |
| US8069405B1 (en) | 2001-11-19 | 2011-11-29 | Cypress Semiconductor Corporation | User interface for efficiently browsing an electronic document using data-driven tabs |
| US6971004B1 (en) | 2001-11-19 | 2005-11-29 | Cypress Semiconductor Corp. | System and method of dynamically reconfiguring a programmable integrated circuit |
| US7844437B1 (en) | 2001-11-19 | 2010-11-30 | Cypress Semiconductor Corporation | System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit |
| US8103497B1 (en) | 2002-03-28 | 2012-01-24 | Cypress Semiconductor Corporation | External interface for event architecture |
| US7308608B1 (en) | 2002-05-01 | 2007-12-11 | Cypress Semiconductor Corporation | Reconfigurable testing system and method |
| US7073099B1 (en) * | 2002-05-30 | 2006-07-04 | Marvell International Ltd. | Method and apparatus for improving memory operation and yield |
| US7761845B1 (en) | 2002-09-09 | 2010-07-20 | Cypress Semiconductor Corporation | Method for parameterizing a user module |
| US7231488B2 (en) * | 2003-09-15 | 2007-06-12 | Infineon Technologies Ag | Self-refresh system and method for dynamic random access memory |
| US6988237B1 (en) | 2004-01-06 | 2006-01-17 | Marvell Semiconductor Israel Ltd. | Error-correction memory architecture for testing production errors |
| JP4478974B2 (ja) * | 2004-01-30 | 2010-06-09 | エルピーダメモリ株式会社 | 半導体記憶装置及びそのリフレッシュ制御方法 |
| US7583551B2 (en) | 2004-03-10 | 2009-09-01 | Micron Technology, Inc. | Power management control and controlling memory refresh operations |
| US7295049B1 (en) * | 2004-03-25 | 2007-11-13 | Cypress Semiconductor Corporation | Method and circuit for rapid alignment of signals |
| US7099221B2 (en) | 2004-05-06 | 2006-08-29 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
| US20060010339A1 (en) | 2004-06-24 | 2006-01-12 | Klein Dean A | Memory system and method having selective ECC during low power refresh |
| US7340668B2 (en) | 2004-06-25 | 2008-03-04 | Micron Technology, Inc. | Low power cost-effective ECC memory system and method |
| US7116602B2 (en) | 2004-07-15 | 2006-10-03 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
| US6965537B1 (en) * | 2004-08-31 | 2005-11-15 | Micron Technology, Inc. | Memory system and method using ECC to achieve low power refresh |
| US7332976B1 (en) | 2005-02-04 | 2008-02-19 | Cypress Semiconductor Corporation | Poly-phase frequency synthesis oscillator |
| KR100691489B1 (ko) * | 2005-03-31 | 2007-03-09 | 주식회사 하이닉스반도체 | 반도체 기억 소자의 테스트용 셀프 리프레쉬 주기 선택회로 및 방법 |
| US7400183B1 (en) | 2005-05-05 | 2008-07-15 | Cypress Semiconductor Corporation | Voltage controlled oscillator delay cell and method |
| US7135909B1 (en) | 2005-05-17 | 2006-11-14 | Sigmatel, Inc. | Temperature sensor circuit and system |
| US8089461B2 (en) | 2005-06-23 | 2012-01-03 | Cypress Semiconductor Corporation | Touch wake for electronic devices |
| US7565479B2 (en) * | 2005-08-04 | 2009-07-21 | Rambus Inc. | Memory with refresh cycle donation to accommodate low-retention-storage rows |
| US7734866B2 (en) * | 2005-08-04 | 2010-06-08 | Rambus Inc. | Memory with address-differentiated refresh rate to accommodate low-retention storage rows |
| US7444577B2 (en) * | 2005-08-04 | 2008-10-28 | Rambus Inc. | Memory device testing to support address-differentiated refresh rates |
| US8085067B1 (en) | 2005-12-21 | 2011-12-27 | Cypress Semiconductor Corporation | Differential-to-single ended signal converter circuit and method |
| JP2007179639A (ja) * | 2005-12-27 | 2007-07-12 | Elpida Memory Inc | 半導体記憶装置 |
| US8067948B2 (en) | 2006-03-27 | 2011-11-29 | Cypress Semiconductor Corporation | Input/output multiplexer bus |
| WO2008018989A2 (en) * | 2006-08-04 | 2008-02-14 | Marvell World Trade Ltd. | Fully- buffered dual in-line memory module with fault correction |
| TWI453751B (zh) * | 2006-08-04 | 2014-09-21 | Marvell World Trade Ltd | 具有誤差修正功能之完全緩衝式雙直列記憶體模組 |
| US7894289B2 (en) * | 2006-10-11 | 2011-02-22 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
| US7900120B2 (en) | 2006-10-18 | 2011-03-01 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
| US20080239852A1 (en) * | 2007-03-28 | 2008-10-02 | Reza Jazayeri | Test feature to improve DRAM charge retention yield |
| US8026739B2 (en) | 2007-04-17 | 2011-09-27 | Cypress Semiconductor Corporation | System level interconnect with programmable switching |
| US8130025B2 (en) | 2007-04-17 | 2012-03-06 | Cypress Semiconductor Corporation | Numerical band gap |
| US7737724B2 (en) * | 2007-04-17 | 2010-06-15 | Cypress Semiconductor Corporation | Universal digital block interconnection and channel routing |
| US8092083B2 (en) | 2007-04-17 | 2012-01-10 | Cypress Semiconductor Corporation | Temperature sensor with digital bandgap |
| US8516025B2 (en) | 2007-04-17 | 2013-08-20 | Cypress Semiconductor Corporation | Clock driven dynamic datapath chaining |
| US20080259703A1 (en) * | 2007-04-17 | 2008-10-23 | Cypress Semiconductor Corp. | Self-timed synchronous memory |
| US8111577B2 (en) | 2007-04-17 | 2012-02-07 | Cypress Semiconductor Corporation | System comprising a state-monitoring memory element |
| US9564902B2 (en) | 2007-04-17 | 2017-02-07 | Cypress Semiconductor Corporation | Dynamically configurable and re-configurable data path |
| US8040266B2 (en) | 2007-04-17 | 2011-10-18 | Cypress Semiconductor Corporation | Programmable sigma-delta analog-to-digital converter |
| US8065653B1 (en) | 2007-04-25 | 2011-11-22 | Cypress Semiconductor Corporation | Configuration of programmable IC design elements |
| US9720805B1 (en) | 2007-04-25 | 2017-08-01 | Cypress Semiconductor Corporation | System and method for controlling a target device |
| US8266575B1 (en) | 2007-04-25 | 2012-09-11 | Cypress Semiconductor Corporation | Systems and methods for dynamically reconfiguring a programmable system on a chip |
| US7545698B2 (en) * | 2007-06-28 | 2009-06-09 | Intel Corporation | Memory test mode for charge retention testing |
| US8049569B1 (en) | 2007-09-05 | 2011-11-01 | Cypress Semiconductor Corporation | Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes |
| US7755960B2 (en) * | 2007-12-17 | 2010-07-13 | Stmicroelectronics Sa | Memory including a performance test circuit |
| US7742355B2 (en) * | 2007-12-20 | 2010-06-22 | Agere Systems Inc. | Dynamic random access memory with low-power refresh |
| US7773441B2 (en) * | 2008-06-18 | 2010-08-10 | Micron Technology, Inc. | Memory malfunction prediction system and method |
| US8008894B2 (en) * | 2008-12-05 | 2011-08-30 | Agiga Tech Inc. | Adjusting a top charge capacitor voltage according to an operating temperature of the capacitor |
| US7990795B2 (en) * | 2009-02-19 | 2011-08-02 | Freescale Semiconductor, Inc. | Dynamic random access memory (DRAM) refresh |
| US9448964B2 (en) | 2009-05-04 | 2016-09-20 | Cypress Semiconductor Corporation | Autonomous control in a programmable system |
| US8116139B2 (en) * | 2010-01-29 | 2012-02-14 | Sandisk Technologies Inc. | Bit line stability detection |
| KR20120005820A (ko) * | 2010-07-09 | 2012-01-17 | 주식회사 하이닉스반도체 | 반도체 장치 및 이의 테스트 방법 |
| US8767493B2 (en) * | 2011-06-27 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM differential voltage sensing apparatus |
| US9159396B2 (en) * | 2011-06-30 | 2015-10-13 | Lattice Semiconductor Corporation | Mechanism for facilitating fine-grained self-refresh control for dynamic memory devices |
| US8848471B2 (en) * | 2012-08-08 | 2014-09-30 | International Business Machines Corporation | Method for optimizing refresh rate for DRAM |
| US8902677B2 (en) * | 2012-12-10 | 2014-12-02 | Freescale Semiconductor, Inc. | Reducing the power consumption of memory devices |
| US9076499B2 (en) | 2012-12-28 | 2015-07-07 | Intel Corporation | Refresh rate performance based on in-system weak bit detection |
| WO2014113572A1 (en) * | 2013-01-16 | 2014-07-24 | Maxlinear, Inc. | Dynamic random access memory for communications systems |
| US9536626B2 (en) | 2013-02-08 | 2017-01-03 | Intel Corporation | Memory subsystem I/O performance based on in-system empirical testing |
| US9224450B2 (en) | 2013-05-08 | 2015-12-29 | International Business Machines Corporation | Reference voltage modification in a memory device |
| US9245604B2 (en) | 2013-05-08 | 2016-01-26 | International Business Machines Corporation | Prioritizing refreshes in a memory device |
| JP6653129B2 (ja) | 2014-05-29 | 2020-02-26 | 株式会社半導体エネルギー研究所 | 記憶装置 |
| US9947386B2 (en) * | 2014-09-21 | 2018-04-17 | Advanced Micro Devices, Inc. | Thermal aware data placement and compute dispatch in a memory system |
| KR102272132B1 (ko) | 2014-12-26 | 2021-07-01 | 삼성전자주식회사 | 반도체 장치 및 그 구동 방법 |
| GB2560968B (en) * | 2017-03-30 | 2020-07-29 | Advanced Risc Mach Ltd | Control of refresh operation for memory regions |
| CN107742526A (zh) * | 2017-09-13 | 2018-02-27 | 上海华为技术有限公司 | 一种刷新周期的调整方法、ddr控制器及ddr系统 |
| US10572183B2 (en) * | 2017-10-18 | 2020-02-25 | Advanced Micro Devices, Inc. | Power efficient retraining of memory accesses |
| US12020740B2 (en) * | 2018-06-26 | 2024-06-25 | Rambus Inc. | Memory device having non-uniform refresh |
| KR102479500B1 (ko) * | 2018-08-09 | 2022-12-20 | 에스케이하이닉스 주식회사 | 메모리 장치, 메모리 시스템 및 그 메모리 장치의 리프레시 방법 |
| CN109920467B (zh) * | 2019-02-28 | 2021-09-07 | 无锡中微腾芯电子有限公司 | 一种用于多存储芯片测试的方法 |
| US11243586B2 (en) * | 2020-02-21 | 2022-02-08 | Dell Products L.P. | System and method for optimizing system power and performance with high power memory modules |
| US11195568B1 (en) | 2020-08-12 | 2021-12-07 | Samsung Electronics Co., Ltd. | Methods and systems for controlling refresh operations of a memory device |
| CN112837728B (zh) * | 2021-03-10 | 2023-05-02 | 群联电子股份有限公司 | 存储器控制方法、存储器存储装置及存储器控制电路单元 |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6061992A (ja) * | 1983-09-14 | 1985-04-09 | Nec Corp | 擬似スタティックメモリ |
| JPS60212896A (ja) * | 1984-04-06 | 1985-10-25 | Hitachi Micro Comput Eng Ltd | ダイナミツク型ｒａｍ |
| JPH0766660B2 (ja) | 1985-03-25 | 1995-07-19 | 株式会社日立製作所 | ダイナミツク型ｒａｍ |
| JPH05266657A (ja) * | 1992-03-23 | 1993-10-15 | Nec Corp | ダイナミック型半導体メモリ |
| JP3285611B2 (ja) * | 1992-06-24 | 2002-05-27 | 富士通株式会社 | ダイナミック半導体メモリ装置 |
| AU6988494A (en) * | 1993-05-28 | 1994-12-20 | Rambus Inc. | Method and apparatus for implementing refresh in a synchronous dram system |
| US5446695A (en) * | 1994-03-22 | 1995-08-29 | International Business Machines Corporation | Memory device with programmable self-refreshing and testing methods therefore |
| KR0122107B1 (ko) | 1994-06-04 | 1997-12-05 | 김광호 | 저전력 셀프리프레쉬 및 번-인 기능을 가지는 반도체메모리장치 |
| WO1996028825A1 (en) * | 1995-03-15 | 1996-09-19 | Hitachi, Ltd. | Semiconductor memory |
| KR0172234B1 (ko) * | 1995-03-24 | 1999-03-30 | 김주용 | 셀프 리프레쉬 주기 조절장치 |
| US5593903A (en) | 1996-03-04 | 1997-01-14 | Motorola, Inc. | Method of forming contact pads for wafer level testing and burn-in of semiconductor dice |
| US5991214A (en) * | 1996-06-14 | 1999-11-23 | Micron Technology, Inc. | Circuit and method for varying a period of an internal control signal during a test mode |
| US6167544A (en) * | 1998-08-19 | 2000-12-26 | Stmicroelectronics, Inc. | Method and apparatus for testing dynamic random access memory |
| KR100363105B1 (ko) | 1998-12-23 | 2003-02-19 | 주식회사 하이닉스반도체 | 셀 리키지 커런트 보상용 셀프 리프레쉬 장치 |
| US6483764B2 (en) | 2001-01-16 | 2002-11-19 | International Business Machines Corporation | Dynamic DRAM refresh rate adjustment based on cell leakage monitoring |
| JP2002324397A (ja) * | 2001-04-26 | 2002-11-08 | Mitsubishi Electric Corp | ダイナミックメモリのリフレッシュ方式 |
| JP2002367370A (ja) * | 2001-06-07 | 2002-12-20 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US6438057B1 (en) | 2001-07-06 | 2002-08-20 | Infineon Technologies Ag | DRAM refresh timing adjustment device, system and method |
| US6646942B2 (en) * | 2001-10-09 | 2003-11-11 | Micron Technology, Inc. | Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages |
-
2003
- 2003-02-19 US US10/369,985 patent/US6778457B1/en not_active Expired - Lifetime
-
2004
- 2004-02-06 KR KR1020057015413A patent/KR20050109501A/ko not_active Ceased
- 2004-02-06 CN CN200480004373A patent/CN100587834C/zh not_active Expired - Fee Related
- 2004-02-06 JP JP2006503386A patent/JP4652324B2/ja not_active Expired - Lifetime
- 2004-02-06 WO PCT/US2004/003492 patent/WO2004075256A2/en not_active Ceased
- 2004-02-19 TW TW093104090A patent/TWI321321B/zh not_active IP Right Cessation
- 2004-06-28 US US10/878,956 patent/US6862240B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9564207B2 (en) | 2015-02-13 | 2017-02-07 | SK Hynix Inc. | Semiconductor memory device, semiconductor memory system and method for controlling self refresh cycle thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4652324B2 (ja) | 2011-03-16 |
| US20040233706A1 (en) | 2004-11-25 |
| TW200502952A (en) | 2005-01-16 |
| TWI321321B (en) | 2010-03-01 |
| JP2006518531A (ja) | 2006-08-10 |
| WO2004075256A3 (en) | 2004-11-25 |
| WO2004075256A2 (en) | 2004-09-02 |
| US6778457B1 (en) | 2004-08-17 |
| CN1751356A (zh) | 2006-03-22 |
| CN100587834C (zh) | 2010-02-03 |
| US6862240B2 (en) | 2005-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6778457B1 (en) | Variable refresh control for a memory | |
| US6646942B2 (en) | Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages | |
| KR100887527B1 (ko) | 동적 랜덤 액세스 메모리 디바이스의 확장된 리프레시 기간동안의 전력 소비 감축을 위한 시스템 및 방법 | |
| US6314028B1 (en) | Semiconductor memory device capable of stable sensing operation | |
| KR100298432B1 (ko) | 반도체메모리장치의전력소비제어회로와이를이용한비트라인프리차지전압가변방법 | |
| KR100284468B1 (ko) | Dram의글로벌비트라인을이용한싱글-엔드센싱 | |
| US6829185B2 (en) | Method for precharging memory cells of a dynamic semiconductor memory during power-up and semiconductor memory | |
| US7663952B2 (en) | Capacitor supported precharging of memory digit lines | |
| US5426601A (en) | Semiconductor memory device having a prolonged data holding time | |
| US6603693B2 (en) | DRAM with bias sensing | |
| US5331595A (en) | Semiconductor memory device having IO line pair to be equalized and divided into blocks and operating method thereof | |
| US20030016564A1 (en) | Semiconductor memory with precharge control | |
| KR100499407B1 (ko) | 휘발성 반도체 메모리 장치 | |
| KR20030057825A (ko) | 비트 라인 프리차지 전압 발생 회로 | |
| KR20040053589A (ko) | 반도체 메모리소자의 비트라인 센스앰프 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
Patent event date: 20050819 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20090206 Comment text: Request for Examination of Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20100930 Patent event code: PE09021S01D |
|
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20110531 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20100930 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |