KR20050010268A - 반도체칩 표면실장방법 - Google Patents

반도체칩 표면실장방법 Download PDF

Info

Publication number
KR20050010268A
KR20050010268A KR1020030049311A KR20030049311A KR20050010268A KR 20050010268 A KR20050010268 A KR 20050010268A KR 1020030049311 A KR1020030049311 A KR 1020030049311A KR 20030049311 A KR20030049311 A KR 20030049311A KR 20050010268 A KR20050010268 A KR 20050010268A
Authority
KR
South Korea
Prior art keywords
semiconductor chip
semiconductor
circuit board
printed circuit
wafer
Prior art date
Application number
KR1020030049311A
Other languages
English (en)
Other versions
KR100520080B1 (ko
Inventor
장세영
박민영
홍순민
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR10-2003-0049311A priority Critical patent/KR100520080B1/ko
Priority to JP2004101334A priority patent/JP2005039206A/ja
Priority to US10/822,669 priority patent/US20050012208A1/en
Publication of KR20050010268A publication Critical patent/KR20050010268A/ko
Application granted granted Critical
Publication of KR100520080B1 publication Critical patent/KR100520080B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

본 발명은, 전자부품이 장착되는 인쇄회로기판에 반도체 칩을 표면실장하는 반도체 칩 표면실장방법에 관한 것으로, 다수의 반도체 칩이 일체로 배열된 반도체 웨이퍼의 배면에 각 반도체의 도전접촉부에 솔더범퍼를 형성하는 단계와; 상기 반도체 웨이퍼의 상기 솔더범퍼가 형성된 면에 언더필 재료를 도포하는 단계와; 상기 언더필 재료를 점착성을 갖는 상태로 부분경화시키는 단계와; 상기 반도체 웨이퍼를 다수의 반도체 칩으로 절단하여 상기 언더필 재료가 상기 인쇄회로기판에 향하도록 상기 반도체 칩을 상기 인쇄회로기판에 배치하는 단계와; 상기 인쇄회로기판을 소정의 온도에서 가열하는 가열단계를 포함하는 것을 특징으로 한다. 이에 의하여, 반도체 칩의 중간단계 이동을 위한 포장재의 필요 없이 공정을 단순화 할 수 있는 반도체 칩 표면실장방법이 제공된다.

Description

반도체칩 표면실장방법{Surface Mounting Method of Semi-conduct Chip on PCB}
본 발명은 반도체 칩 표면실장방법에 관한 것으로, 보다 상세하게는 반도체 칩의 중간단계 이동을 위한 포장재의 필요 없이 공정을 단순화할 수 있는 반도체 칩 표면실장방법에 관한 것이다.
최근들어 전자기기의 박형화, 소형화 추세에 따라 반도체 소자를 외부환경으로부터 보호하는 기능의 패키징 기술에 있어서 고속, 고밀도 실장등이 요구되며, 이러한 요구에 부응하여 리드프레임이 없는 플립칩 실장기술이 등장하게 되었다.
플립칩 실장기술은 반도체 칩을 패키징하지 않고 그대로 인쇄회로기판에 실장하는 기술로, 반도체 칩에 범퍼를 형성하고 범퍼와 인쇄회로기판에 인쇄된 접속패드를 솔더링 방식으로 접속시키는 기술을 말한다. 이와 같은 방법으로 인쇄회로기판에 반도체 칩을 실장하면 반도체 칩의 범퍼의 높이로 인해 반도체 칩과 인쇄회로기판 사이에 간극이 발생되어 반도체 칩의 지지력이 약화된다. 따라서 반도체 칩을 안정적으로 지지하기 위해 반도체 칩과 인쇄회로기판 사이에 발생된 간극에 액상수지 물질의 언더필 재료를 주입하고 경화시켜 반도체 칩을 지지하는 언더필 층을 형성함으로써 본딩 수행능력과 칩의 손상 및 열전달 능력이 향상되어 진다.
도 1은 종래기술에 따른 반도체 칩의 표면실장방법을 나타낸 흐름도이고, 도 2는 도 1에 따른 표면실장방법을 도시한 간략도이다. 도면에 도시된 바와 같이, 반도체 칩의 표면실장방법은 솔버범퍼의 형성단계(S10), 웨이퍼 절단단계(S20), 반도체 칩의 이동수단에 적재단계(S30), 반도체 칩의 배치단계(S40), 리플로우 단계(S50), 언더필 주입단계(S60), 언더필 경화단계(S70)를 거친다.
솔더범퍼의 형성단계(S10)는 웨이퍼(100)상의 활성면에 전기적인 접점을 형성할 수 있도록 솔더범퍼(210)를 웨이퍼(100)상에 형성된 패턴에 따라 형성하는 단계이다. 이어 웨이퍼 절단단계(S20)는 솔더범퍼(210)가 형성된 웨이퍼(100)를 소정크기의 반도체 칩(200)으로 절단하는 단계이다. 절단된 반도체 칩(200)을 이동수단에 적재하는 단계(S30)에서는 반도체 칩(200)을 이후 공정으로 이동할 때 반도체 칩(200)의 손상을 막기 위해 이동수단에 적재하는 단계를 말한다. 여기서 이동수단으로는 칩 트레이(110) 또는 피더 테이프(120)가 주로 사용된다. 일반적으로 이상의 단계까지는 반도체 제조업체에서 수행이 되며 상술한 바와 같이 칩 트레이(110) 또는 피더 테이프(120) 상태로 전자제품 업체의 실장공정으로 옮겨지게 된다.
이어 칩 트레이(110) 또는 피더 테이프(120)에 의해 이동된 반도체 칩(200)은 인쇄회로기판(400)에 배치된다(S40). 이때, 인쇄회로기판(400)에는 반도체 칩(200) 이외의 전자부품(300, 수동소자, 커넥터 등)이 혼재되어 실장 된다. 여기서 반도체 칩(200)은 후술할 언더필 재료(220)의 주입을 위해 타 전자부품(300)들과 최소 2mm 이상의 최소 간격을 유지하여 배치되어야 한다. 반도체 칩(200)이 배치된 인쇄회로기판(400)은 소정온도에서 가열되는 리플로우 단계(S50)를 거치게 되는데, 이때 반도체 칩(200)의 솔더범퍼(210)가 리플로우 되면서 인쇄회로기판(400)의 전극과 전기적으로 연결된다. 리플로우 단계(S50)의 가열온도는 솔더범퍼(210)의 재질에 따라 결정된다.
리플로우 단계(S50)가 끝나면, 솔더범퍼(210)에 의해 발생된 반도체 칩(200)과 인쇄회로기판(400) 사이의 간극에 언더필 재료(220)를 주입한다(S60). 언더필 재료(220)를 주입하기 위해서 반도체 칩(200)과 다른 전자부품(300)들 간의 거리가 최소거리 이상 확보되어야 하는 것은 상술한 바이다.
주입된 언더필 재료(220)를 경화시키기 위해 소정온도에서 다시 인쇄회로기판(400)을 가열하는 경화단계(S70)가 끝나면 인쇄회로기판(400)에 반도체 칩(200)이 기타 전자부품(300)들과 함께 혼재되어 표면실장이 된다.
하지만 종래기술에 의한 반도체 칩 표면실장방법에 있어서, 반도체 칩(200)을 인쇄회로기판(400)에 장착하고 리플로우로 접합을 형성한 후 언더필 재료(220)를 개별적으로 주입하고 경화하기 때문에 표면실장공정과 표면실장장비가 복잡해지면서 공정시간이 길게 소요되는 문제점이 있다. 또한, 반도체 칩(200)과 주변 전자부품(300) 간의 최소간격을 유지해야 하므로 고밀도 실장이 어려운 문제점이 있다.
또한, 칩 트레이(110) 또는 피더 테이프(200)를 사용하는 경우에 웨이퍼(100)에서 이와 같은 중간 포장용기에 담는 공정이 한 번 더 필요하고 다시 표면실장공정에서 칩 트레이(110)나 피더 테이프(120)에서 인쇄회로기판(400)으로 반도체 칩(200)을 장착하는 공정이 필요하게 되므로 많은 공정을 거치게 된다. 또한, 칩 트레이(110) 또는 피더 테이프(120)에 의해 운반될 경우 반도체 칩(200)에 형성된 솔더범퍼(210)가 손상되는 문제점 등이 있다.
따라서 본 발명의 목적은 이와 같은 종래의 문제점을 해결하기 위한 것으로서, 반도체 칩의 중간단계 이동을 위한 포장재가 필요 없고, 단순화된 공정의 반도체 칩 표면실장방법을 제공함에 있다.
도 1은 종래기술에 따른 반도체 칩 표면실장방법을 도시한 흐름도,
도 2는 도1에 따른 반도체 칩 표면실장방법을 도시한 간략도,
도 3은 본 발명에 따른 반도체 칩 표면실장방법을 도시한 흐름도,
도 4는 도 1에 따른 반도체 칩 표면실장방법을 도시한 간략도이다.
<도면의 주요 부분에 대한 부호의 설명>
1: 반도체 웨이퍼 2: 반도체 칩
4: 인쇄회로기판 11: 칩 트레이
12; 피더 테이프 21: 솔더범퍼
22: 언더필 재료
상기 목적은, 본 발명에 따라, 전자부품이 장착되는 인쇄회로기판에 반도체 칩을 표면실장하는 반도체 칩 표면실장방법에 있어서, 다수의 반도체 칩이 일체로 배열된 반도체 웨이퍼의 배면에 각 반도체의 도전접촉부에 솔더범퍼를 형성하는 단계와; 상기 반도체 웨이퍼의 상기 솔더범퍼가 형성된 면에 언더필 재료를 도포하는 단계와; 상기 언더필 재료를 점착성을 갖는 상태로 부분경화시키는 단계와; 상기 반도체 웨이퍼를 다수의 반도체 칩으로 절단하여 상기 언더필 재료가 상기 인쇄회로기판에 향하도록 상기 반도체 칩을 상기 인쇄회로기판에 배치하는 단계와; 상기 인쇄회로기판을 소정의 온도에서 가열하는 가열단계를 포함하는 것을 특징으로 하는 반도체 칩 표면실장방법에 의해 달성된다.
여기서, 상기 가열단계의 가열온도는 상기 솔더범퍼의 용융점 이상으로 되는 것이 솔더범퍼를 리플로우 함과 동시에, 언더필 재료를 경화시킬 수 있다.
도 3은 본 발명에 따른 반도체 칩 표면실장방법을 나타낸 흐름도이고, 도 4는 도 3에 따른 표면실장방법을 도시한 간략도이다.
도면에 도시된 바와 같이, 반도체 칩 표면실장은 솔더범퍼 형성단계(S1), 언더필도포단계(S2), 언더필 부분경화단계(S3), 웨이퍼 절단단계(S4), 반도체 칩 배치단계(S5), 가열단계(S6)를 거치게 된다.
솔더범퍼 형성단계(S1)는 웨이퍼(1)에 형성된 패턴에 따라 인쇄회로기판(4)과 전기적으로 접촉할 수 있도록 웨이퍼(1)상의 활성면에 솔더범퍼(21)를 형성하는 단계이다. 일반적으로 솔더범퍼(21)는 Sn/Pb의 합금이 많이 사용된다.
이어 솔더범퍼(21)가 형성된 웨이퍼(1) 면에 언더필 재료(22)를 도포하는 언더필 도포단계(S2)를 거친다. 언더필 재료(22)를 도포하는 방법으로는 스텐실 프린팅법, 스핀 코팅법, 디핑법등을 이용할 수 있다. 이때 언더필 재료(22)의 도포 두께는 언더필 재료(22)의 특성에 따라 차이가 날 수 있으나, 일반적으로솔더범퍼(21)가 인쇄회로기판(4)과의 전기적 접촉이 원활하게 이루어 질 수 있도록 솔더범퍼(21)의 높이에 대하여 같거나 낮게 도포된다. 하지만, 후술할 가열단계에서 언더필 재료(22)의 특성에 따라 솔더범퍼(21)가 리플로우 될 때 언더필 재료(22)를 뚫고 인쇄회로기판(4)에 전기적으로 접촉이 가능할 수도 있으므로, 솔더범퍼(21)의 높이에 대하여 높게 언더필 재료(22)가 도포될 수도 있음은 물론이다.
웨이퍼(1)상에 도포된 언더필 재료(22)는 부분경화단계(S3)를 거쳐 점착성을 갖는 상태로 된다. 부분경화단계(S3)에서 언더필 재료(22)가 도포된 웨이퍼(1)는 소정온도에 노출이 되어 언더필 재료(22)가 부분경화된다. 언더필 재료(22)를 부분경화하는 이유는 언더필 재료(22)는 액상으로 웨이퍼(1) 상에 도포되므로 웨이퍼(1)를 운반할 때 언더필 재료(22)가 흘러내려 운반에 어려움이 있기 때문이다. 또한, 언더필 재료(22)는 소정의 접착력이 있으므로 후술할 가열단계에서 경화되어 인쇄회로기판(4)과 반도체 칩(2)을 접착시켜주는 역할을 하기 때문이다. 일반적으로 이상의 단계까지는 반도체 제조업체에서 수행이 되며 언더필 재료(22)가 부분경화된 웨이퍼(1) 상태로 전자제품 업체의 실장공정으로 옮겨지게 된다.
이어, 반도체 웨이퍼(1)를 반도체 칩(2)으로 절단하는 절단단계(S4)를 거친다. 절단단계(S4)를 거친 반도체 칩(2)의 각각에는 솔더범퍼(21)와 부분경화상태의 언더필 재료(22)가 마련되어 있게 된다.
절단된 반도체 칩(2)은 전자부품(3)이 실장되는 인쇄회로기판(4)에 배치된다. 여기서, 인쇄회로기판(4)에 전자부품(3)과 동시에 배치될 수도 있으며, 전자부품(3)에 대하여 먼저 또는 나중에 인쇄회로기판(4)에 반도체 칩(1)이 배치될 수도 있어 배치 순서에 구속되지 않는다.
반도체 칩(2)이 배치된 인쇄회로기판(4)은 소정온도에서 가열되어, 솔더범퍼(21)의 리플로우와 언더필 재료(22)의 경화가 이루어진다(S6). 가열온도는 언더필 재료(22)와 솔더범퍼(21)의 재료 특성에 따라 달라지겠지만, 일반적으로 솔더범퍼(21)의 용융점 온도 보다는 높게 설정되어야 한다. 솔더범퍼(21)의 리플로우와 언더필 재료(22)의 경화가 이루어지는 과정을 살펴보면, 솔더범퍼(21)가 소정온도 이상으로 가열되면, 솔더범퍼(21)가 유동성을 가지게 되고, 솔더범퍼(21)는 인쇄회로기판(4)의 접점과 전기적으로 접촉하게 된다. 또한, 언더필 재료(22)는 온도가 올라감에 따라 경화가 이루어져 고상으로 되고, 가열 단계가 끝나게 되면 솔더범퍼(21)는 다시 굳게 되어 인쇄회로기판(4)과 안정적으로 전기적인 연결이 이루어진다.
따라서 모든 공정이 끝나게 되면, 언더필 재료(22)는 경화가 이루어져, 인쇄회로기판(4)과 반도체 칩(2)을 지지하고, 소정의 접착력으로 인쇄회로기판(4)과 반도체 칩(2)의 상호 결합을 도와준다. 한편 언더필 재료(22)는 솔더범퍼(21)의 주성분인 Pb속에 포함되는 소량의 방사선 원소에 의해 방사되는 알파선으로 인하여 반도체 칩(2) 소자에 노이즈가 인가되어 오동작을 유발시키므로, 노이즈를 차단하는 역할을 하기도 한다.
이상의 설명에서 반도체 칩의 표면실장에 있어서, 플립 칩 실장에 대하여 설명하였으나, WLCSP(Wafer Level Chip Size Package) 기술에도 이용될 수 있음은 물론이다. WLCSP란 칩과 패키기 사이의 와이어 본딩, 플립칩본딩등의 접속기술 대신에 입방체화하기 전에 플립칩과 같은 원리로 반도체 전공정의 배선기술을 사용하여 칩 패드와 외부단자를 결선하는 것을 말한다.
이상 설명한 바와 같이, 본 발명에 따르면, 반도체 칩의 중간단계 이동을 위한 포장재의 필요 없이 공정을 단순화할 수 있는 반도체 칩 표면실장방법이 제공된다.

Claims (2)

  1. 전자부품이 장착되는 인쇄회로기판에 반도체 칩을 표면실장하는 반도체 칩 표면실장방법에 있어서,
    다수의 반도체 칩이 일체로 배열된 반도체 웨이퍼의 배면에 각 반도체의 도전접촉부에 솔더범퍼를 형성하는 단계와;
    상기 반도체 웨이퍼의 상기 솔더범퍼가 형성된 면에 언더필 재료를 도포하는 단계와;
    상기 언더필 재료를 점착성을 갖는 상태로 부분경화시키는 단계와;
    상기 반도체 웨이퍼를 다수의 반도체 칩으로 절단하여 상기 언더필 재료가 상기 인쇄회로기판에 향하도록 상기 반도체 칩을 상기 인쇄회로기판에 배치하는 단계와;
    상기 인쇄회로기판을 소정의 온도에서 가열하는 가열단계를 포함하는 것을 특징으로 하는 반도체 칩 표면실장방법.
  2. 제1항에 있어서,
    상기 가열단계의 가열온도는 상기 솔더범퍼의 용융점 이상인 것을 특징으로 하는 반도체 칩 표면실장방법.
KR10-2003-0049311A 2003-07-18 2003-07-18 반도체칩 표면실장방법 KR100520080B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR10-2003-0049311A KR100520080B1 (ko) 2003-07-18 2003-07-18 반도체칩 표면실장방법
JP2004101334A JP2005039206A (ja) 2003-07-18 2004-03-30 半導体チップ表面実装方法
US10/822,669 US20050012208A1 (en) 2003-07-18 2004-04-13 Method of surface-mounting semiconductor chip on PCB

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2003-0049311A KR100520080B1 (ko) 2003-07-18 2003-07-18 반도체칩 표면실장방법

Publications (2)

Publication Number Publication Date
KR20050010268A true KR20050010268A (ko) 2005-01-27
KR100520080B1 KR100520080B1 (ko) 2005-10-12

Family

ID=34056907

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2003-0049311A KR100520080B1 (ko) 2003-07-18 2003-07-18 반도체칩 표면실장방법

Country Status (3)

Country Link
US (1) US20050012208A1 (ko)
JP (1) JP2005039206A (ko)
KR (1) KR100520080B1 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008069805A1 (en) * 2006-12-08 2008-06-12 Henkel Ag & Co. Kgaa Process for coating a bumped semiconductor wafer
WO2021182790A1 (ko) * 2020-03-10 2021-09-16 엘지이노텍 주식회사 인쇄회로기판

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005046280B4 (de) * 2005-09-27 2007-11-08 Infineon Technologies Ag Halbleiterbauteil mit einem Halbleiterchip sowie Verfahren zur Herstellung desselben
US20100007018A1 (en) * 2006-12-08 2010-01-14 Derek Wyatt Process for coating a bumped semiconductor wafer
US7867793B2 (en) * 2007-07-09 2011-01-11 Koninklijke Philips Electronics N.V. Substrate removal during LED formation
US10153180B2 (en) * 2013-10-02 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor bonding structures and methods
US9478443B2 (en) 2014-08-28 2016-10-25 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package and method of forming the same
US9337154B2 (en) * 2014-08-28 2016-05-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of manufacturing the same
US9502364B2 (en) * 2014-08-28 2016-11-22 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package and method of forming the same
JP2018113414A (ja) * 2017-01-13 2018-07-19 新光電気工業株式会社 半導体装置とその製造方法
CN110704471B (zh) * 2019-10-21 2023-01-06 深圳市展祥通信科技有限公司 一种物料管理方法、物料管理系统及电子设备
TW202244104A (zh) * 2021-01-20 2022-11-16 日商積水化學工業股份有限公司 非導電性助焊劑、連接構造體及連接構造體之製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3468386B2 (ja) * 1995-04-17 2003-11-17 カシオ計算機株式会社 半導体装置の製造方法
JP3038703B2 (ja) * 1995-07-20 2000-05-08 カシオ計算機株式会社 半導体装置およびその製造方法並びにその実装方法
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
US6201301B1 (en) * 1998-01-21 2001-03-13 Lsi Logic Corporation Low cost thermally enhanced flip chip BGA
US6746896B1 (en) * 1999-08-28 2004-06-08 Georgia Tech Research Corp. Process and material for low-cost flip-chip solder interconnect structures
KR100674501B1 (ko) * 1999-12-24 2007-01-25 삼성전자주식회사 플립 칩 본딩 기술을 이용한 반도체 칩 실장 방법
US6537482B1 (en) * 2000-08-08 2003-03-25 Micron Technology, Inc. Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography
WO2002058108A2 (en) * 2000-11-14 2002-07-25 Henkel Loctite Corporation Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith
US6507119B2 (en) * 2000-11-30 2003-01-14 Siliconware Precision Industries Co., Ltd. Direct-downset flip-chip package assembly and method of fabricating the same
US6582990B2 (en) * 2001-08-24 2003-06-24 International Rectifier Corporation Wafer level underfill and interconnect process
US7015066B2 (en) * 2001-09-05 2006-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008069805A1 (en) * 2006-12-08 2008-06-12 Henkel Ag & Co. Kgaa Process for coating a bumped semiconductor wafer
WO2021182790A1 (ko) * 2020-03-10 2021-09-16 엘지이노텍 주식회사 인쇄회로기판

Also Published As

Publication number Publication date
KR100520080B1 (ko) 2005-10-12
JP2005039206A (ja) 2005-02-10
US20050012208A1 (en) 2005-01-20

Similar Documents

Publication Publication Date Title
US6356453B1 (en) Electronic package having flip chip integrated circuit and passive chip component
US6546620B1 (en) Flip chip integrated circuit and passive chip component package fabrication method
KR100553853B1 (ko) 반도체 장치, 반도체 장치의 제조 방법 및 반도체 장치의적층 방법
US6133064A (en) Flip chip ball grid array package with laminated substrate
US6553660B2 (en) Electronic device and a method of manufacturing the same
KR100424382B1 (ko) 열확산기를 부착한 반도체 장치 및 그 제조 방법
KR20100009941A (ko) 단차를 갖는 몰딩수지에 도전성 비아를 포함하는 반도체패키지, 그 형성방법 및 이를 이용한 적층 반도체 패키지
KR100520080B1 (ko) 반도체칩 표면실장방법
EP1430532B1 (en) Encapsulation of pin solder for maintaining accuracy in pin position
KR20020044577A (ko) 개선된 플립-칩 결합 패키지
KR20140095406A (ko) 플립칩 부품의 수지 밀봉 방법
US8168525B2 (en) Electronic part mounting board and method of mounting the same
JP4018936B2 (ja) 回路モジュールの製造方法
KR20080074468A (ko) 초음파를 이용한 반도체 칩의 표면실장방법
KR20010063682A (ko) 플립 칩 본딩 기술을 이용한 반도체 칩 실장 방법
US20050196907A1 (en) Underfill system for die-over-die arrangements
KR100665288B1 (ko) 플립칩 패키지 제조방법
KR20120062434A (ko) 반도체 패키지 및 그 제조방법
JP2009277838A (ja) 半導体装置の製造方法、基板トレイ、及び基板収納装置
KR100199851B1 (ko) 칩 스케일 패키지 및 그의 제조 방법
KR20030095036A (ko) 플립 칩 패키지의 솔더 범프 연결방법
KR20070063119A (ko) 플립칩 실장용 기판의 제조방법
JP2008022016A (ja) 回路モジュール
CN115410931A (zh) Ic载板连接结构及其制作方法
JP2005268704A (ja) 半導体装置、半導体装置の実装方法及び半導体装置を有する電子機器

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120831

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20130902

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee