KR20020041758A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

Info

Publication number
KR20020041758A
KR20020041758A KR1020010074144A KR20010074144A KR20020041758A KR 20020041758 A KR20020041758 A KR 20020041758A KR 1020010074144 A KR1020010074144 A KR 1020010074144A KR 20010074144 A KR20010074144 A KR 20010074144A KR 20020041758 A KR20020041758 A KR 20020041758A
Authority
KR
South Korea
Prior art keywords
field effect
effect transistor
semiconductor
semiconductor region
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020010074144A
Other languages
English (en)
Korean (ko)
Inventor
아오노히데끼
오꾸야마고우스께
와따나베고우조우
구로다겐이찌
Original Assignee
가나이 쓰토무
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쓰토무, 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가나이 쓰토무
Publication of KR20020041758A publication Critical patent/KR20020041758A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/8312—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/83138—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different shapes or dimensions of their gate conductors

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020010074144A 2000-11-28 2001-11-27 반도체 장치 및 그 제조 방법 Withdrawn KR20020041758A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2000-00361548 2000-11-28
JP2000361548A JP2002164442A (ja) 2000-11-28 2000-11-28 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
KR20020041758A true KR20020041758A (ko) 2002-06-03

Family

ID=18832968

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010074144A Withdrawn KR20020041758A (ko) 2000-11-28 2001-11-27 반도체 장치 및 그 제조 방법

Country Status (4)

Country Link
US (1) US7067888B2 (enExample)
JP (1) JP2002164442A (enExample)
KR (1) KR20020041758A (enExample)
TW (1) TW518745B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347423A (ja) * 2002-05-28 2003-12-05 Renesas Technology Corp 半導体集積回路装置およびその製造方法
US6844573B1 (en) * 2002-08-28 2005-01-18 Advanced Micro Devices, Inc Structure for minimizing hot spots in SOI device
WO2004054078A1 (en) * 2002-12-10 2004-06-24 Koninklijke Philips Electronics N.V. Integrated half-bridge power circuit
TWI257175B (en) * 2004-11-25 2006-06-21 Chunghwa Picture Tubes Ltd Production of lightly doped drain of low-temperature poly-silicon thin film transistor
CN100447964C (zh) * 2004-11-26 2008-12-31 中华映管股份有限公司 薄膜晶体管的制作方法
US7183159B2 (en) * 2005-01-14 2007-02-27 Freescale Semiconductor, Inc. Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices
US9990459B2 (en) 2016-03-18 2018-06-05 International Business Machines Corporation Checking wafer-level integrated designs for antenna rule compliance
US10346580B2 (en) 2016-03-25 2019-07-09 International Business Machines Corporation Checking wafer-level integrated designs for rule compliance

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3095564B2 (ja) * 1992-05-29 2000-10-03 株式会社東芝 半導体装置及び半導体装置の製造方法
JP2859288B2 (ja) * 1989-03-20 1999-02-17 株式会社日立製作所 半導体集積回路装置及びその製造方法
US5572480A (en) * 1990-02-09 1996-11-05 Hitachi Ltd. Semiconductor integrated circuit device and process for fabricating the same
KR100199258B1 (ko) * 1990-02-09 1999-06-15 가나이 쓰도무 반도체집적회로장치
JP3474589B2 (ja) * 1992-04-17 2003-12-08 株式会社デンソー 相補型ｍｉｓトランジスタ装置
JP3055424B2 (ja) * 1994-04-28 2000-06-26 株式会社デンソー Ｍｉｓ型半導体装置の製造方法
US5650340A (en) * 1994-08-18 1997-07-22 Sun Microsystems, Inc. Method of making asymmetric low power MOS devices
JP3008154B2 (ja) * 1994-12-19 2000-02-14 セイコーインスツルメンツ株式会社 半導体装置の製造方法
JP3239202B2 (ja) * 1995-12-01 2001-12-17 シャープ株式会社 Ｍｏｓトランジスタ及びその製造方法
EP0814502A1 (en) * 1996-06-21 1997-12-29 Matsushita Electric Industrial Co., Ltd. Complementary semiconductor device and method for producing the same
JP3544833B2 (ja) * 1997-09-18 2004-07-21 株式会社東芝 半導体装置及びその製造方法
TW451317B (en) * 2000-03-24 2001-08-21 Vanguard Int Semiconduct Corp Manufacturing method of asymmetrical source/drain of DRAM cell
JP2001351383A (ja) * 2000-06-07 2001-12-21 Mitsubishi Electric Corp 半導体集積回路装置

Also Published As

Publication number Publication date
TW518745B (en) 2003-01-21
JP2002164442A (ja) 2002-06-07
US20020063284A1 (en) 2002-05-30
US7067888B2 (en) 2006-06-27

Similar Documents

Publication Publication Date Title
US20070040222A1 (en) Method and apparatus for improved ESD performance
US20120061761A1 (en) Semiconductor integrated circuit device and manufacturing method for semiconductor integrated circuit devices
KR20010033347A (ko) 벌크 씨모스 구조와 양립 가능한 에스오아이 구조
JP2001352077A (ja) Ｓｏｉ電界効果トランジスタ
US8643100B2 (en) Field effect transistor having multiple effective oxide thicknesses and corresponding multiple channel doping profiles
US20170336467A1 (en) Gate protection for hv-stress application
JPH0210678Y2 (enExample)
KR20020041758A (ko) 반도체 장치 및 그 제조 방법
US9337310B2 (en) Low leakage, high frequency devices
US8735994B2 (en) Electrical-free dummy gate
US10373862B2 (en) Semiconductor device
KR950006985B1 (ko) 반도체 집적 회로 장치
US6537893B2 (en) Substrate isolated transistor
US7692210B2 (en) Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same
US20100163985A1 (en) Semiconductor and method for manufacturing the same
US6831337B2 (en) Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (“ESD”) protection
US6730582B2 (en) Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (ESD) protection
US8319286B2 (en) System and method for input pin ESD protection with floating and/or biased polysilicon regions
US6156609A (en) EEPROM device manufacturing method
JP2004266019A (ja) 半導体装置及びその製造方法
CN1996593B (zh) 利用浮动和/或偏置多晶硅区域的静电保护系统和方法
Li et al. The Hot Carrier Injection Induced Degradation in MOS Transistors with Subthreshold Hump and the Corelated Impacts on Low Frequency Noise for Low Power Analog Designs
KR930001562B1 (ko) 반도체 집적 회로장치의 제조방법
KR100520142B1 (ko) 높은 문턱전압 트랜지스터
JP2795243B2 (ja) マスクパターン設計方法

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20011127

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid