KR20000045440A - Method for forming contact of semiconductor device - Google Patents
Method for forming contact of semiconductor device Download PDFInfo
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- KR20000045440A KR20000045440A KR1019980061998A KR19980061998A KR20000045440A KR 20000045440 A KR20000045440 A KR 20000045440A KR 1019980061998 A KR1019980061998 A KR 1019980061998A KR 19980061998 A KR19980061998 A KR 19980061998A KR 20000045440 A KR20000045440 A KR 20000045440A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 식가장벽의 식각선택비를 증가시켜 고집적 소자의 콘택 형성시에 적합하도록한 반도체소자의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact of a semiconductor device, which is suitable for forming a contact of a highly integrated device by increasing an etching selectivity of an edible barrier.
종래의 반도체소자의 콘택홀 형성방법에는 직접 콘택홀 형성방법과 측벽스페이서를 사용하여 절연을 진행하는 콘택홀 형성방법과 자기정렬 콘택홀 형성방법 등이 있다.Conventional contact hole forming methods for semiconductor devices include a direct contact hole forming method, a contact hole forming method for performing insulation using sidewall spacers, and a self-aligning contact hole forming method.
이 중 직접 콘택홀과 측벽 스페이서 콘택홀 형성방법은 리소그래피 공정의 해상(resolution)한계와 오버레이 정확도 한계로 인하여 0.3 μm 이하의 디자인 룰을 갖는 소자제조에는 그 사용에 불가하다.Among them, the direct contact hole and sidewall spacer contact hole forming method cannot be used for device manufacturing having a design rule of 0.3 μm or less due to the resolution limit of the lithography process and the limitation of overlay accuracy.
자기정렬 공정에는 산화막 식각시에 식각 장벽막으로 사용하는 물질에 따라 폴리를 이용하는 자기정렬과 질화막을 이용하는 자기정렬이 있다.In the self-alignment process, there is a self-alignment using poly and a self-alignment using a nitride film depending on the material used as an etch barrier film in etching an oxide film.
폴리를 이용하는 자기정렬에는 다시 산화막 식각시 식각장벽막으로 폴리실리콘을 전면에 증착하여 사용하는 폴리장벽 자기정렬과 콘택홀이 형성될 지역에만 패드모양으로 형성하는 패드폴리 자기정렬이 있다.In the self alignment using poly, there is a poly barrier self alignment used by depositing polysilicon on the front surface as an etch barrier when etching an oxide layer and a pad poly self alignment in a pad shape only in an area where a contact hole is to be formed.
폴리를 이용하는 자기정렬은 산화막 식각기구와 다른 식각기구를 갖는 폴리를 사용하기 때문에 산화막 식각시 폴리에 대하여 매우 높은 식각 선택비를 용이하게 형성할 수 있는 장점이 있다.Self-alignment using poly has an advantage of easily forming a very high etching selectivity with respect to poly when the oxide is etched since the poly having a etch mechanism different from the oxide etch mechanism is used.
그러나, 폴리장벽 자기정렬의 경우 콘택홀간의 절연 문제가 있고 패드폴리자기정렬의 경우에는 콘택패드와 실리콘기판간에 정렬 불량이 발생하였을때 Si 기판의 손상이 발생하는 문제가 있다.However, in the case of polybarrier self-alignment, there is a problem of insulation between contact holes, and in the case of pad poly-magnetic alignment, there is a problem of damage to the Si substrate when misalignment occurs between the contact pad and the silicon substrate.
패드 폴리자기정렬에서는 실리콘기판의 손상 방지를 위하여 스페이서를 사용하는 방법과 폴리머를 사용하는 방법등으로 콘택홀패드를 확장시키는 방법이 제시되고 있다.In pad poly magnetic alignment, contact hole pads have been proposed to expand the contact hole pads using a spacer and a polymer to prevent damage to the silicon substrate.
그러나, 질화막을 사용하는 자기정렬은 산화막 식각시에 질화막에 대하여 고선택비를 확보하기 위하여 지나치게 많은 폴리머 유발가스를 사용하기 때문에 공정 재현성 문제와 좁은 공정 윈도우 문제 및 경사콘택 형성으로 인한 좁은 콘택 면적 문제등이 발생한다.However, since the self-alignment using nitride film uses too much polymer induced gas to secure high selectivity for nitride film during oxide etching, process reproducibility problem, narrow process window problem, and narrow contact area problem due to inclined contact formation Etc.
이외에 질화막을 사용하므로써 발생할 수 있는 문제로 질화막에 의한 스트레스가 있다. 이러한 질화막에 의한 스트레스를 개선하기 위한 방법으로는 질화막 대신에 산화막을 사용하는 방법이 있다.In addition, a problem caused by using a nitride film is stress caused by the nitride film. As a method for improving the stress caused by the nitride film, there is a method of using an oxide film instead of the nitride film.
그러나, 보통의 산화막을 사용할 경우, 산화막 식각시 산화막에 대하여 높은 식각선택비를 확보하는 것은 최근 기술에서는 매우 어렵다.However, in the case of using an ordinary oxide film, it is very difficult in the recent technology to secure a high etching selectivity with respect to the oxide film during the oxide film etching.
이에, 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 콘택 형성시에 실리콘리치산화막에 대한 높은 식각선택비를 확보할 수 있는 반도체소자의 콘택 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a contact of a semiconductor device capable of securing a high etching selectivity for a silicon rich oxide film during contact formation. .
또한, 본 발명의 다른 목적은 식각방지층으로 질화막 사용시에 발생하는 스트레스에 의한 소자 특성의 악화를 방지할 수 있는 반도체소자의 콘택 형성방법을 제공함에 있다.In addition, another object of the present invention is to provide a method for forming a contact of a semiconductor device capable of preventing deterioration of device characteristics due to stress generated when a nitride film is used as an etch stop layer.
상기 목적을 달성하기 위한 본 발명은, 실리콘기판상에 워드라인용 폴리실리콘층과 하드 마스크용 실리콘리치산화막을 증착하고 이를 선택적으로 제거하여 워드라인과 실리콘리치산화막패턴을 형성하는 공정과;According to an aspect of the present invention, there is provided a method of forming a word line and a silicon rich oxide film pattern by depositing a polysilicon layer for a word line and a silicon rich oxide film for a hard mask and selectively removing the silicon silicon oxide film on a silicon substrate;
상기 워드라인과 실리콘리치산화막패턴을 포함한 전체 구조의 상부에 실리콘리치산화막을 형성하는 공정과;Forming a silicon rich oxide film on the entire structure including the word line and the silicon rich oxide film pattern;
상기 실리콘리치산화막 상부에 BPSG막을 형성하고 그 위에 콘택마스크용 감광막패턴을 형성하는 공정과;Forming a BPSG film on the silicon rich oxide film and forming a contact mask photoresist pattern thereon;
상기 감광막패턴을 마스크로 상기 BPSG막을 선택적으로 제거하여 콘택홀을 형성하는 공정을 포함하여 구성되는 것을 제1특징으로한다.The first feature is that the method comprises forming a contact hole by selectively removing the BPSG film using the photoresist pattern as a mask.
또한, 본 발명에 따른 반도체소자의 콘택 형성방법은, 실리콘기판상에 워드라인용 폴리실리콘층과 하드 마스크용 실리콘리치산화막을 증착하고 이를 선택적으로 제거하여 워드라인과 실리콘리치산화막패턴을 형성하는 공정과;In addition, in the method for forming a contact of a semiconductor device according to the present invention, a process of forming a word line and a silicon rich oxide pattern by depositing a polysilicon layer for a word line and a silicon rich oxide film for a hard mask on a silicon substrate and selectively removing it and;
상기 워드라인과 실리콘리치산화막패턴의 측면에 산화막스페이서를 형성하는 공정과;Forming an oxide film spacer on side surfaces of the word line and the silicon rich oxide film pattern;
상기 스페이서와 실리콘리치산화막패턴상부를 포함한 전체 구조의 상부에 실리콘리치산화막을 형성하는 공정과;Forming a silicon rich oxide film on the entire structure including the spacer and the upper portion of the silicon rich oxide film pattern;
상기 실리콘리치산화막상부에 BPSG막을 형성하고 그 위에 콘택마스크용 감광막패턴을 형성하는 공정과;Forming a BPSG film on the silicon rich oxide film and forming a contact mask photoresist pattern thereon;
상기 감광막패턴을 마스크로 상기 BPSG막을 선택적으로 제거하여 콘택홀을 형성하는 공정을 포함하여 구성되는 것을 제2특징으로한다.The second feature is that the step of forming a contact hole by selectively removing the BPSG film using the photosensitive film pattern as a mask.
그리고, 본 발명에 따른 반도체소자의 콘택 형성방법은, 실리콘기판상에 워드라인용 폴리실리콘층과 하드 마스크용실리콘리치산화막을 증착하고 이를 선택적으로 제거하여 워드라인과 실리콘리치산화막패턴을 형성하는 공정과;In the method for forming a contact of a semiconductor device according to the present invention, a process of forming a word line and a silicon rich oxide pattern by depositing a polysilicon layer for a word line and a silicon rich oxide film for a hard mask and selectively removing the silicon silicon oxide layer on a silicon substrate and;
상기 워드라인과 실리콘리치산화막패턴의 측면에 실리콘리치산화막을 형성하는 공정과;Forming a silicon rich oxide film on side surfaces of the word line and the silicon rich oxide film pattern;
상기 실리콘리치산화막스페이서와 실리콘리치산화막패턴상부를 포함한 전체 구조의 상부에 BPSG막을 형성하고 그 위에 콘택마스크용 감광막패턴을 형성하는 공정과;Forming a BPSG film on an upper portion of the entire structure including the silicon rich oxide spacers and the upper portions of the silicon rich oxide film patterns, and forming a photoresist pattern for contact masks thereon;
상기 감광막패턴을 마스크로 상기 BPSG막을 선택적으로 제거하여 콘택홀을 형성하는 공정을 포함하여 구성되는 것을 제3특징으로한다.And a step of forming a contact hole by selectively removing the BPSG film using the photoresist pattern as a mask.
본 발명의 기술적 요지는, 반도체소자의 콘택홀을 Si-리치 산화막을 사용한 자기정렬 콘택홀 형성기술로 형성할 경우에 산화막 식각 기구와 다른 식각 기구를 갖는 Si을 산화막에 첨가하므로써 산화막 식각시 산화막 식각 장벽으로 사용하는 Si-리치 산화막에 대한 식각선택비를 증가시켜 공정 여유를 확보할 수 있다.The technical gist of the present invention is that when the contact hole of a semiconductor device is formed by a self-aligned contact hole formation technique using a Si-rich oxide film, the oxide film is etched during the etching of the oxide film by adding Si having an etching mechanism different from that of the oxide device to the oxide film. The process margin can be secured by increasing the etching selectivity of the Si-rich oxide film used as a barrier.
도 1 내지 도 3 은 본 발명의 제1실시예에 따른 반도체소자의 콘택 형성공정 단면도이다.1 to 3 are cross-sectional views of a contact forming process of a semiconductor device according to a first embodiment of the present invention.
도 4 는 본 발명의 제2실시예에 따른 반도체소자의 콘택홀형성단면도이다.4 is a cross-sectional view illustrating the formation of a contact hole in a semiconductor device according to a second exemplary embodiment of the present invention.
도 5 는 본 발명의 제3실시예에 따른 반도체소자의 콘택홀형성단면도이다.5 is a cross-sectional view illustrating a contact hole forming of a semiconductor device in accordance with a third embodiment of the present invention.
＜도면의주요부분에대한부호설명＞<Description of Signs of Main Parts of Drawings>
1, 11, 21 : 워드라인 2, 12, 22 : 실리콘리치산화막패턴1, 11, 21: word line 2, 12, 22: silicon rich oxide pattern
3, 13, 23 : 실리콘리치산화막 4, 15, 24 : BPSG막3, 13, 23: silicon rich oxide film 4, 15, 24: BPSG film
4a, 15a, 24a : 콘택홀4a, 15a, 24a: contact hole
이하, 본 발명의 실시예들에 따른 반도체소자의 콘택 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method for forming a contact of a semiconductor device according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 3 은 본 발명의 제1실시예에 따른 반도체소자의 콘택 형성공정 단면도이다.1 to 3 are cross-sectional views of a contact forming process of a semiconductor device according to a first embodiment of the present invention.
도 4 는 본 발명의 제2실시예에 따른 반도체소자의 콘택홀형성단면도이다.4 is a cross-sectional view illustrating the formation of a contact hole in a semiconductor device according to a second exemplary embodiment of the present invention.
도 5 는 본 발명의 제3실시예에 따른 반도체소자의 콘택홀형성단면도이다.5 is a cross-sectional view illustrating a contact hole forming of a semiconductor device in accordance with a third embodiment of the present invention.
본 발명의 제1실시예에 따른 반도체소자의 콘택 형성방법은, 먼저 도 1 에 도시된 바와같이, 실리콘기판(미도시)상에 워드라인용 폴리실리콘층과 하드마스크용 실리콘리치 산화막을 순차적으로 증착하고 그위에 워드라인마스크용 감광막패턴(미도시)을 형성한다.In the method for forming a contact of a semiconductor device according to the first embodiment of the present invention, first, as shown in FIG. 1, a polysilicon layer for a word line and a silicon rich oxide film for a hard mask are sequentially formed on a silicon substrate (not shown). And a photoresist pattern (not shown) for a word line mask is formed thereon.
그다음, 상기 제1감광막패턴(미도시)을 마스크로 상기 제1실리콘리치 산화막과 폴리실리콘층을 노광 및 현상공정을 진행한후 이를 선택적으로 패터닝하여 워드라인(1)과 하드마스크용 실리콘리치산화막패턴(2)을 형성한다.Subsequently, the first silicon rich oxide film and the polysilicon layer are exposed and developed using the first photoresist pattern (not shown) as a mask, and then selectively patterned to form the word line 1 and the silicon rich oxide film for hard mask. The pattern 2 is formed.
이어서, 상기 제1감광막패턴(미도시)을 제거하고, 도 2 에 도시된 바와같이, 상기 상기 워드라인(1)과 실리콘리치산화막패턴(2)을 포함한 전체 구조의 상부에 산화막 식각시의 식각장벽으로 사용하기 위해 실리콘리치산화막(3)을 형성한다.Subsequently, the first photoresist layer pattern (not shown) is removed, and as shown in FIG. 2, the etching process is performed when the oxide layer is etched on the entire structure including the word line 1 and the silicon rich oxide layer pattern 2. A silicon rich oxide film 3 is formed for use as a barrier.
이때, 상기 실리콘리치산화막(3)은 PECVD(Plasma enhanced chemical vapor deposition) 또는 고밀도 플라즈마 CVD 방법을 사용하여 형성한다.In this case, the silicon rich oxide film 3 is formed using a plasma enhanced chemical vapor deposition (PECVD) or a high density plasma CVD method.
또한, 상기 실리콘리치산화막(3)은 실리콘 함량을 조절하여 식각선택비를 조절한다.In addition, the silicon rich oxide film 3 controls the etching selectivity by controlling the silicon content.
그다음, 전체 구조의 상부에 BPSG막(4)을 형성하여 평탄화공정을 진행하고, 그 위에 콘택홀마스크용 제2감광막패턴(5)을 형성한다.Next, a BPSG film 4 is formed on the entire structure to perform a planarization process, and a second photoresist film pattern 5 for a contact hole mask is formed thereon.
이어서, 상기 제2감광막패턴(5)을 마스크로 상기 BPSG막(4)을 패터닝하여 상기 BPSG막(4)에 콘택홀(4a)을 형성한다.Subsequently, the BPSG film 4 is patterned using the second photoresist film pattern 5 to form a contact hole 4a in the BPSG film 4.
이때, 실리콘리치산화막에 대하여 높은 식각선택비를 확보할 수 있도록 C4F8과 같은 다량의 폴리머 유발가스를 사용한다.In this case, a large amount of polymer induced gas such as C 4 F 8 is used to secure a high etching selectivity with respect to the silicon rich oxide film.
또한, 상기 BPSG막 식각시에 실리콘리치산화막에 대한 높은 식각선택비를 확보하기 위해 CH3F, C2F6,C3F8, C4, C2F4, C2CF5등 C-F 계 가스 또는 C-H-F 계 가스를 사용한다.In addition, CF 3 F, C 2 F 6, C 3 F 8 , C 4 , C 2 F 4 , C 2 CF 5 and other CF systems in order to secure a high etching selectivity for the silicon rich oxide film during the etching of the BPSG film Gas or CHF-based gas is used.
그리고, 상기 BPSG막 식각시에 Ar, Ne, He, Xe 등의 불활성 가스를 첨가하여 사용하거나 H2, C2H2,CH3F, CH2F2등 수소를 포함한 가스를 사용할 수도 있다.In addition, an inert gas such as Ar, Ne, He, or Xe may be added to the BPSG film during etching, or a gas containing hydrogen such as H 2 , C 2 H 2, CH 3 F, or CH 2 F 2 may be used.
그다음, 도면에는 도시하지 않았지만, 상기 실리콘리치산화막(3)을 식각하여 콘택홀(4a)을 연다. 이때, 상기 실리콘리치 산화막(3)은 콘택홀(4a)내에서 스페이서(미도시)로 형성되어 워드라인(1)을 절연시킨다.Next, although not shown in the drawing, the silicon rich oxide film 3 is etched to open the contact hole 4a. In this case, the silicon rich oxide layer 3 is formed as a spacer (not shown) in the contact hole 4a to insulate the word line 1.
또한, 본 발명의 제2실시예는, 도 4 에 도시된 바와같이, 실리콘기판(미도시)상에 워드라인용 폴리실리콘층과 하드마스크용 실리콘리치 산화막을 순차적으로 증착하고 그위에 워드라인마스크용 감광막패턴(미도시)을 형성한다.In addition, according to the second embodiment of the present invention, as shown in FIG. 4, a polysilicon layer for a word line and a silicon rich oxide film for a hard mask are sequentially deposited on a silicon substrate (not shown), and a word line mask is disposed thereon. A photosensitive film pattern (not shown) is formed.
그다음, 상기 제1감광막패턴(미도시)을 마스크로 상기 제1실리콘리치 산화막과 폴리실리콘층을 노광 및 현상공정을 진행한후 이를 선택적으로 패터닝하여 워드라인(11)과 하드마스크용 실리콘리치산화막패턴(12)을 형성한다.Subsequently, the first silicon rich oxide film and the polysilicon layer are exposed and developed using the first photoresist pattern (not shown) as a mask, and then selectively patterned to form the word line 11 and the silicon rich oxide film for hard mask. The pattern 12 is formed.
이어서, 상기 제1감광막패턴(미도시)을 제거하고, 상기 워드라인(11)과 실리콘리치산화막패턴(12)을 포함한 전체 구조의 상부에 산화막을 증착하고 이를 이방성 식각공정에 의해 식각하여 상기 워드라인(11)과 실리콘리치산화막패턴(12)의 측면에 산화막스페이서(13)를 형성한다.Subsequently, the first photoresist layer pattern (not shown) is removed, an oxide layer is deposited on the entire structure including the word line 11 and the silicon rich oxide layer pattern 12, and the oxide layer is etched by an anisotropic etching process. An oxide film spacer 13 is formed on the side of the line 11 and the silicon rich oxide film pattern 12.
그다음, 실시예 1에서 사용한 증착방법을 사용하여 상기 전체 구조의 상부에 실리콘리치산화막(14)을 형성하고, 그 위에 BPSG막(15)을 형성하여 평탄화공정을 진행하고, 도면에는 도시하지 않았지만, 그 위에 콘택홀마스크용 제2감광막패턴(미도시)을 형성한다.Next, the silicon rich oxide film 14 is formed on the entire structure by using the vapor deposition method used in Example 1, and the BPSG film 15 is formed thereon to proceed the planarization process. A second photoresist pattern (not shown) for a contact hole mask is formed thereon.
이어서, 실시예 1 에서 사용한 식각가스를 사용하여 상기 감광막패턴(미도시)을 마스크로 상기 BPSG막(15)을 패터닝하여 콘택홀(15a)을 형성한다.Subsequently, the contact hole 15a is formed by patterning the BPSG film 15 using the photoresist pattern (not shown) as a mask using the etching gas used in Example 1. FIG.
그다음, 도면에는 도시하지 않았지만, 상기 실리콘리치산화막(14)을 식각하여 콘택홀(15a)을 열므로써 워드라인(11)을 절연시킨다.Next, although not shown in the drawing, the silicon rich oxide layer 14 is etched to open the contact hole 15a to insulate the word line 11.
그리고, 본 발명의 제3 실시예는, 도 5 에 도시된 바와같이, 실리콘기판(미도시)상에 워드라인용 폴리실리콘층과 하드마스크용 제1실리콘리치산화막을 순차적으로 증착하고 상기 제1실리콘리치산화막상부에 워드라인마스크용 감광막패턴(미도시)을 형성한다.According to a third embodiment of the present invention, as shown in FIG. 5, a polysilicon layer for a word line and a first silicon rich oxide layer for a hard mask are sequentially deposited on a silicon substrate (not shown). A photoresist pattern (not shown) for a word line mask is formed on the silicon rich oxide film.
그다음, 상기 제1감광막패턴(미도시)을 마스크로 상기 제1실리콘리치 산화막과 폴리실리콘층을 노광 및 현상공정을 진행한후 이를 선택적으로 패터닝하여 워드라인(21)과 하드마스크용 실리콘리치산화막패턴(22)을 형성한다.Subsequently, the first silicon rich oxide film and the polysilicon layer are exposed and developed using the first photoresist pattern (not shown) as a mask, and then selectively patterned to form a word line 21 and a silicon rich oxide film for a hard mask. The pattern 22 is formed.
이어서, 상기 제1감광막패턴(미도시)을 제거하고, 상기 워드라인(21)과 실리콘리치산화막패턴(22)을 포함한 전체 구조의 상부에 제2 실리콘리치산화막(미도시)을 증착하고 이를 이방성 식각공정에 의해 식각하여 상기 워드라인(21)과 실리콘리치산화막패턴(22)의 측면에 실시예1에서 사용한 증착방법을 사용하여 실리콘리치산화막스페이서(23)를 형성한다.Subsequently, the first photoresist layer pattern (not shown) is removed, and a second silicon rich oxide layer (not shown) is deposited on top of the entire structure including the word line 21 and the silicon rich oxide layer pattern 22. The silicon rich oxide spacer 23 is formed on the side of the word line 21 and the silicon rich oxide layer pattern 22 using the deposition method used in Example 1 by etching.
그다음, 상기 전체 구조의 상부에 BPSG막(24)을 형성하여 평탄화공정을 진행하고, 도면에는 도시하지 않았지만, 그 위에 콘택홀마스크용 제2감광막패턴(미도시)을 형성한다.Next, a BPSG film 24 is formed on the entire structure to perform a planarization process, and although not shown in the drawing, a second photoresist film pattern (not shown) for a contact hole mask is formed thereon.
이어서, 실시예 1에서 사용한 식각가스를 이용하여 상기 감광막패턴(미도시)을 마스크로 상기 BPSG막(24)을 패터닝하여 콘택홀(24a)을 형성한다. 이때, 상기 콘택홀(24a) 형성시에 실리콘리치산화막스페이서(23)는 워드라인(21)을 절연시킨다.Next, the contact hole 24a is formed by patterning the BPSG film 24 using the photoresist pattern (not shown) as a mask using the etching gas used in the first embodiment. At this time, the silicon rich oxide spacer 23 insulates the word line 21 when the contact hole 24a is formed.
상기한 바와같이, 본 발명에 따른 반도체소자의 콘택 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the contact forming method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 실리콘리치산화막을 산화막의 식각시에 식각장벽으로 사용하여 실리콘리치 산화막에 대하여 높은 식각 선택비를 확보할 수 있으므로, 종래의 질화막을 식각장벽으로 사용할 경우에 발생하는 스트레스에 의한 소자 특성의 악화를 방지할 수 있다.In the present invention, since the silicon rich oxide film is used as an etch barrier at the time of etching the oxide film, a high etching selectivity can be ensured with respect to the silicon rich oxide film, so that the element caused by stress generated when the conventional nitride film is used as the etching barrier. The deterioration of a characteristic can be prevented.
또한, 본 발명에 있어서는 산화막 식각시에 실리콘리치산화막에 대한 높은 식각 선택비를 확보하고 보다 안정된 플라즈마 유지와 실리콘리치 펀치쓰로우(punch-through) 및 에칭스톱(etch stop)을 개선시키고 프로세스 윈도우(window)를 확장시킬 수 있다.In addition, the present invention ensures a high etching selectivity for the silicon rich oxide film during the etching of the oxide, improves more stable plasma retention, improves silicon-rich punch-through and etch stop, and improves the process window. window) can be extended.
Claims (19)
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| KR20040041252A (en) * | 2002-11-09 | 2004-05-17 | 삼성전자주식회사 | Magnetic enhanced reactive ion etching process for manufacturing method of semiconductor device |
| KR100438660B1 (en) * | 2001-06-29 | 2004-07-02 | 주식회사 하이닉스반도체 | Method for forming the contact hole of semiconductor device |
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| KR100284133B1 (en) * | 1994-07-28 | 2001-04-02 | 김영환 | Self-aligned contact formation method of semiconductor device |
| JP3555333B2 (en) * | 1996-05-30 | 2004-08-18 | ソニー株式会社 | Method for manufacturing semiconductor device |
| JPH10173049A (en) * | 1996-12-11 | 1998-06-26 | Fujitsu Ltd | Semiconductor device and its manufacture |
| US6136700A (en) * | 1996-12-20 | 2000-10-24 | Texas Instruments Incorporated | Method for enhancing the performance of a contact |
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| KR100438660B1 (en) * | 2001-06-29 | 2004-07-02 | 주식회사 하이닉스반도체 | Method for forming the contact hole of semiconductor device |
| KR20040041252A (en) * | 2002-11-09 | 2004-05-17 | 삼성전자주식회사 | Magnetic enhanced reactive ion etching process for manufacturing method of semiconductor device |
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