KR100438660B1 - Method for forming the contact hole of semiconductor device - Google Patents
Method for forming the contact hole of semiconductor device Download PDFInfo
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- KR100438660B1 KR100438660B1 KR10-2001-0038503A KR20010038503A KR100438660B1 KR 100438660 B1 KR100438660 B1 KR 100438660B1 KR 20010038503 A KR20010038503 A KR 20010038503A KR 100438660 B1 KR100438660 B1 KR 100438660B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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Abstract
본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 특히 워드라인이 형성된 반도체기판 전체에 장벽층을 형성한 후, 층간절연막을 적층하여 셀프얼라인 콘택을 형성함에 있어서, 상기 장벽층을 단일 챔버에서 챔버의 부피를 최소화하고, SiH2가스와 NH3가스를 적절한 비율로 혼합하여 형성하는 것을 특징으로 하여, 후속 셀프얼라인 콘택홀 식각 시, 반도체기판에 인가되는 스트레스가 억제됨으로써, 반도체소자의 특성, 신뢰성을 향상시키고 그에 따른 반도체 소자의 고집적화를 가능하게 하는 기술로 매우 유용하고 효과적인 장점을 지닌 발명에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. In particular, a barrier layer is formed over an entire semiconductor substrate on which a word line is formed, and then an interlayer insulating film is stacked to form a self-aligned contact. Minimizing the volume of the chamber in the mixture, and forming a mixture of SiH 2 gas and NH 3 gas in an appropriate ratio, the stress applied to the semiconductor substrate during subsequent self-aligned contact hole etching is suppressed, thereby reducing the The present invention relates to an invention having a very useful and effective advantage as a technology for improving characteristics, reliability, and thus high integration of semiconductor devices.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게 워드라인이형성된 반도체기판 전체에 장벽층을 형성한 후, 층간절연막을 적층하여 셀프얼라인 콘택을 형성함에 있어서, 상기 장벽층을 단일 챔버에서 챔버의 부피를 최소화하고, SiH2가스와 NH3가스를 적절한 비율로 혼합하여 형성함으로써, 후속 셀프얼라인 콘택홀 식각 시, 반도체기판에 인가되는 스트레스를 억제하여 반도체소자의 특성을 향상시킬 수 있는 반도체소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, after forming a barrier layer on an entire semiconductor substrate on which word lines are formed, and then stacking an interlayer insulating layer to form a self-aligned contact, the barrier layer is formed in a single chamber. By minimizing the volume of the chamber and forming a mixture of SiH 2 gas and NH 3 gas at an appropriate ratio, it is possible to suppress the stress applied to the semiconductor substrate during subsequent self-aligned contact hole etching to improve the characteristics of the semiconductor device. The present invention relates to a method for forming a contact hole in a semiconductor device.
최근 반도체 소자가 점차적으로 고집적화 됨에 따라 반도체 기판 상에 배선의 넓이뿐만 아니라 배선과 배선 사이의 고집적화가 진행됨에 따라 콘택홀 형성에 관한 문제는 크게 대두되고 있다.Recently, as the semiconductor devices are gradually integrated, as the integration of the wirings and the wirings is increased as well as the width of the wirings on the semiconductor substrates, problems related to the formation of contact holes are increasing.
일반적으로 반도체 소자의 고집적화에 따라 셀부에서 비트라인 콘택과 스토리지 노드 콘택 형성을 위하여 게이트라인을 형성한 후 마스크질화막을 이용하여 자기정렬콘택(Self Align Contact)을 형성한다.In general, as the semiconductor device is highly integrated, gate lines are formed in the cell unit to form bit line contacts and storage node contacts, and then self alignment contacts are formed using a mask nitride layer.
종래에는 반도체소자의 콘택홀을 형성함에 있어서, 층간절연막과 실리콘질화막이 접합된 상태에서 약 700℃ 이상의 고온 후속공정을 실시해야 하는 경우가 발생한다. 예를 들어 디램(DRAM) 제조 공정 중 캐패시터 스토리지 노드 콘택을 셀프얼라인 콘택(SAC : Self-Aligned Contact) 공정으로 구현할 경우, 하부의 평탄화 층간절연막인 BPSG막 상에는 배리어(barrier) 혹은 스페이서(spacer)로서 BPSG막과 식각 선택비가 높은 질화막을 사용하게 된다.Conventionally, in forming a contact hole of a semiconductor device, there is a case where a high temperature follow-up process of about 700 ° C. or more must be performed while the interlayer insulating film and the silicon nitride film are bonded to each other. For example, when a capacitor storage node contact is implemented as a self-aligned contact (SAC) process in a DRAM manufacturing process, a barrier or spacer is disposed on a BPSG film, which is a planarization interlayer insulating film underneath. For example, a nitride film having a high etching selectivity with a BPSG film is used.
그리고, 이후에 캐패시터 유전체로서, 열산화막 또는 열질화막을 형성하여야 함으로 고온 공정이 수반되게 된다.After that, a thermal oxide film or a thermal nitride film must be formed as the capacitor dielectric material, so that a high temperature process is involved.
그러데, PECVD에 의한 실리콘질화막과 BPSG막 간의 열팽창계수는 약 10배 정도 차이가 나는 등, BPSG막과 실리콘질화막은 큰 열 팽창계수를 갖기 때문에 두 물질이 접합된 경우 그 계면은 심한 스트레스를 받는 문제점이 있었다.However, the thermal expansion coefficient between the silicon nitride film and the BPSG film by PECVD is about 10 times different. Since the BPSG film and the silicon nitride film have a large coefficient of thermal expansion, the interface is severely stressed when the two materials are bonded. There was this.
또한, 상기와 같이 스트레스를 받은 상태에서 800℃ 정도의 고온 공정을 실시하는 경우, 스트레스를 받는 계면에서는 크랙(crack)이 발생되는 문제점이 있었다.In addition, when performing a high temperature process of about 800 ℃ in a stressed state as described above, there was a problem that a crack (crack) occurs at the interface under stress.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 워드라인이 형성된 반도체기판 전체에 장벽층을 형성한 후, 층간절연막을 적층하여 셀프얼라인 콘택을 형성함에 있어서, 상기 장벽층을 단일 챔버에서 챔버의 부피를 최소화하고, SiH2가스와 NH3가스를 적절한 비율로 혼합하여 형성함으로써, 후속 셀프얼라인 콘택홀 식각 시, 반도체기판에 인가되는 스트레스를 억제하여 반도체소자의 특성을 향상시키도록 하는 것이 목적이다.The present invention has been made to solve the above problems, and an object of the present invention is to form a self-aligned contact by forming an interlayer insulating film after forming a barrier layer on the entire semiconductor substrate on which the word line is formed. The barrier layer is formed by minimizing the volume of the chamber in a single chamber, and mixing the SiH 2 gas and the NH 3 gas in an appropriate ratio, thereby suppressing the stress applied to the semiconductor substrate during subsequent self-aligned contact hole etching. The purpose is to improve the characteristics.
도 1a 내지 도 1b는 본 발명에 따른 반도체소자의 콘택홀 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A through 1B are cross-sectional views sequentially illustrating a method of forming a contact hole in a semiconductor device according to the present invention.
도 2는 종래 반도체소자의 콘택홀 형성방법에 의해 형성된 반도체소자와 본 발명에 따른 반도체소자의 콘택홀 형성방법에 의해 형성된 반도체소자의 스트레스 정도를 비교한 그래프이다.2 is a graph comparing the stress levels of a semiconductor device formed by a contact hole forming method of a conventional semiconductor device and a semiconductor device formed by a contact hole forming method of a semiconductor device according to the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 반도체기판 110 : 워드라인100: semiconductor substrate 110: word line
120 : 장벽층 130 : 층간절연막120: barrier layer 130: interlayer insulating film
140 : 셀프얼라인 콘택140: self-aligned contact
상기 목적을 달성하기 위하여, 본 발명은 반도체소자 제조방법에 있어서, 워드라인이 형성된 반도체기판 상에 단일챔버의 볼륨을 최소화하여 장벽층을 형성하는 단계와; 상기 장벽층 상부에 층간절연막을 적층한 후, 노광 및 식각공정을 진행하여 셀프얼라인 콘택을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 콘택홀 형성방법을 제공한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, the method comprising: forming a barrier layer by minimizing the volume of a single chamber on a semiconductor substrate on which a word line is formed; And forming a self-aligned contact by stacking an interlayer insulating layer on the barrier layer, and performing an exposure and etching process to provide a contact hole forming method of a semiconductor device.
본 발명은 상기 장벽층을 SiH4와, SiCl4및 SiH2Cl2가스 중 어느 하나의 가스와 NH3또는 N2가스를 혼합하여 100 ~ 400 Torr의 압력과 400 ~ 800℃의 온도의 단일챔버에서 LPCVD 방법으로 형성하여 반도체기판에 인가되는 스트레스를 억제하는 것을 특징으로 한다.In the present invention, the barrier layer is mixed with one of SiH 4 , any one of SiCl 4 and SiH 2 Cl 2 gas and NH 3 or N 2 gas to provide a single chamber at a pressure of 100 to 400 Torr and a temperature of 400 to 800 ° C. Formed by the LPCVD method characterized in that to suppress the stress applied to the semiconductor substrate.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1b는 본 발명에 따른 반도체소자의 콘택홀 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A through 1B are cross-sectional views sequentially illustrating a method of forming a contact hole in a semiconductor device according to the present invention.
도 1a에 도시된 바와 같이, 워드라인(110)이 형성된 반도체기판(100) 상에 단일챔버의 볼륨을 최소화하여 SiH4와, SiCl4및 SiH2Cl2가스 중 적어도 어느 하나의 선택된 가스와 NH3또는 N2가스를 혼합하여 LPCVD 방법으로 장벽층(120)을 형성한다.As shown in FIG. 1A, the volume of a single chamber is minimized on the semiconductor substrate 100 on which the word line 110 is formed, and at least one selected from among SiH 4 , SiCl 4, and SiH 2 Cl 2 gases, and NH. 3 or N 2 gas is mixed to form the barrier layer 120 by LPCVD.
이때, 상기 장벽층(120)은 3 ~ 80sccm의 SiH4가스와 1000 ~ 7000sccm의 NH3가스를 혼합하여 100 ~ 400 Torr의 압력과 400 ~ 800℃의 온도의 볼륨이 최소화된 단일챔버에서 형성한다.In this case, the barrier layer 120 is mixed in a SiH 4 gas of 3 ~ 80sccm and NH 3 gas of 1000 ~ 7000sccm is formed in a single chamber with a volume of 100 ~ 400 Torr pressure and 400 ~ 800 ℃ temperature is minimized .
그 결과, 후속 고온 공정 시, LPCVD에 의한 장벽층(120)과 BPSG로 이루어진 층간절연막(미도시함) 간의 열팽창계수가 감소되어 두 물질이 접합된 경우 그 계면의 스트레스를 최소화 할 수 있다.As a result, in the subsequent high temperature process, the coefficient of thermal expansion between the barrier layer 120 and the interlayer insulating film (not shown) made of BPSG by LPCVD is reduced, thereby minimizing the stress at the interface when the two materials are bonded.
그리고, 도 1b에 도시된 바와 같이, 상기 장벽층(120) 상부에 산화계열의 물질을 사용하여 층간절연막(130)을 적층한 후, 상기 장벽층(120)을 식각정지막으로 노광 및 식각공정을 진행하여 셀프얼라인 콘택(140)을 형성한다.As shown in FIG. 1B, after the interlayer insulating layer 130 is laminated using an oxide-based material on the barrier layer 120, the barrier layer 120 is exposed and etched using an etch stop layer. Proceeding to form the self-aligned contact 140.
이때, 상기 셀프얼라인 콘택(140) 형성 시, 워드라인(110) 사이의 셀프얼라인 콘택(140)에 정확한 얼라인을 하기 어렵기 때문에 콘택 사이즈보다 더 크게 식각한다.At this time, when the self-aligned contact 140 is formed, it is difficult to align the self-aligned contact 140 between the word lines 110 more than the contact size.
도 2는 종래 반도체소자의 콘택홀 형성방법에 의해 형성된 반도체소자와 본 발명에 따른 반도체소자의 콘택홀 형성방법에 의해 형성된 반도체소자의 스트레스 정도를 비교한 그래프이다.2 is a graph comparing the stress levels of a semiconductor device formed by a contact hole forming method of a conventional semiconductor device and a semiconductor device formed by a contact hole forming method of a semiconductor device according to the present invention.
도 2에 도시된 바와 같이, 상기와 같은 방법에 의해 형성된 반도체소자 "A"는 종래 기술에 의해 형성된 반도체소자 "B"에 비해 트랜지스터 디그래데이션(degradation)에 의한 Vt 특성 열화가 방지되어 반도체소자의 리프레쉬(refresh)특성을 향상시키고, 제조수율을 증가시킬 수 있다.As shown in FIG. 2, the semiconductor device “A” formed by the above method is prevented from degrading Vt characteristics due to transistor degradation compared to the semiconductor device “B” formed by the prior art, and thus the semiconductor device. It is possible to improve the refresh (refresh) characteristics of the, and increase the production yield.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 콘택홀 형성방법을 이용하게 되면, 워드라인이 형성된 반도체기판 전체에 장벽층을 형성한 후, 층간절연막을 적층하여 셀프얼라인 콘택을 형성함에 있어서, 상기 장벽층을 단일 챔버에서 챔버의 부피를 최소화하고, SiH2가스와 NH3가스를 적절한 비율로 혼합하여 형성함으로써, 후속 셀프얼라인 콘택홀 식각 시, 반도체기판에 인가되는 스트레스를 억제하여 반도체소자의 특성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the contact hole forming method of the semiconductor device according to the present invention is used, a barrier layer is formed on the entire semiconductor substrate on which the word lines are formed, and then an interlayer insulating film is laminated to form a self-aligned contact. The barrier layer is formed by minimizing the volume of the chamber in a single chamber and by mixing SiH 2 gas and NH 3 gas in an appropriate ratio, thereby suppressing stress applied to the semiconductor substrate during subsequent self-aligned contact hole etching. It is a very useful and effective invention for improving the characteristics of semiconductor devices.
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| KR (1) | KR100438660B1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980032877A (en) * | 1996-10-24 | 1998-07-25 | 김영환 | Method for manufacturing contact hole of semiconductor device |
| KR20000032021A (en) * | 1998-11-12 | 2000-06-05 | 김영환 | Method for producing contact hole of semiconductor device |
| KR20000045440A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming contact of semiconductor device |
| KR20010004721A (en) * | 1999-06-29 | 2001-01-15 | 김영환 | Method of manufacturing a semiconductor device |
| KR20010045128A (en) * | 1999-11-03 | 2001-06-05 | 박종섭 | Forming method for self aligned contact of semiconductor device |
-
2001
- 2001-06-29 KR KR10-2001-0038503A patent/KR100438660B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980032877A (en) * | 1996-10-24 | 1998-07-25 | 김영환 | Method for manufacturing contact hole of semiconductor device |
| KR20000032021A (en) * | 1998-11-12 | 2000-06-05 | 김영환 | Method for producing contact hole of semiconductor device |
| KR20000045440A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming contact of semiconductor device |
| KR20010004721A (en) * | 1999-06-29 | 2001-01-15 | 김영환 | Method of manufacturing a semiconductor device |
| KR20010045128A (en) * | 1999-11-03 | 2001-06-05 | 박종섭 | Forming method for self aligned contact of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20030002794A (en) | 2003-01-09 |
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