US20010001702A1 - Method of fabricating an opening with deep ultra-violet photoresist - Google Patents
Method of fabricating an opening with deep ultra-violet photoresist Download PDFInfo
- Publication number
- US20010001702A1 US20010001702A1 US09/076,243 US7624398A US2001001702A1 US 20010001702 A1 US20010001702 A1 US 20010001702A1 US 7624398 A US7624398 A US 7624398A US 2001001702 A1 US2001001702 A1 US 2001001702A1
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- US
- United States
- Prior art keywords
- layer
- hard mask
- opening
- deep ultra
- violet photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
- G03F7/405—Treatment with inorganic or organometallic reagents after imagewise removal
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
Definitions
- the invention relates to a method of fabricating an opening, and more particularly to a method of fabricating an opening formed by deep ultra-violet photoresist (DUV PR).
- DUV PR deep ultra-violet photoresist
- Deep ultra-violet photoresist is necessary for the semiconductor process with the size of 0.25 ⁇ m or less. It can be employed in, for example, oxide layer etching.
- the DUV PR is exposed under a deep ultra-violet light and developed to define the oxide layer.
- An opening for a contact, via or damascene is then formed by developing the DUV PR.
- DUV PR is used to reduce the width of the opening but the material of the DUV PR is soft and not high temperature compatible.
- erosion and reflow of the DUV PR easily occurs while etching the oxide layer which requires high ion energy.
- the side profile of the DUV PR isn't entirely vertical and it is difficult to precisely control the width of the opening.
- a commonly employed method of preventing overetching of the DUV PR is to increase the thickness of the DUV PR.
- the increment of the thickness prevents the photoresist from being properly exposed and successfully developed, because of focus of depth. Therefore increasing the thickness of the DUV PR as described above doesn't solve the problem.
- the width of the opening can be reduced as much as possible to follow the trend towards smaller size .
- the quality of the opening width can also be controlled in a stable fashion.
- the invention is directed towards a method of fabricating an opening with deep ultra-violet photoresist.
- An insulating layer is formed over a substrate where devices are formed thereon.
- a DUV PR layer with a first opening is then formed on the insulating layer.
- a hard mask layer is formed on the DUV PR layer and a second opening is next formed within the insulating layer by using the first opening to define the insulating layer.
- the hard mask is used to protect the DUV PR layer.
- the DUV PR layer and the hard mask are removed to expose the insulating layer and a desired second opening is thus formed.
- FIGS. 1 A- 1 D is a cross sectional view of the formation of an opening in a preferred embodiment according to the invention.
- This invention is about a method of fabricating an opening within the insulating layer
- the opening for the contact, via or damascene can be formed by this invention.
- the example below is made in reference to an opening for a via.
- a substrate 100 has device structures (not shown) and a conductive layer 102 formed on it.
- the conductive layer 102 is, for example, a metal layer or polysilicon with dopant.
- An insulating layer 106 (or dielectric layer), such as a silicon oxide layer, is formed over the substrate 100 .
- a DUV PR layer 106 with an opening 108 is then formed on the insulating layer, with the opening 108 located over a via opening formed within the insulating layer 104 in the subsequent process.
- a hard mask layer 110 is formed on the surface of the DUV PR 106 .
- the hard mask layer 110 includes a silicon layer, which is formed by silylation. If a plasma treatment is performed after silylation, the silicon layer can become an oxide layer or a nitride layer as oxygen or nitrogen is pumped into the plasma chamber.
- the opening 108 within the DUV PR 110 is used to define the insulating layer 104 , and an opening 112 is then formed within the insulating layer 104 , exposing the surface of the conductive layer 102 as shown in FIG. 2C.
- the opening 112 can be formed by dry etching.
- the material character of the DUV PR 106 is soft, and as previously mentioned, suffers erosion and reflow by etchant as the opening 112 is formed within the insulating layer 104 . This makes it impossible to achieve a thoroughly vertical opening 112 .
- the hard mask layer 110 is deliberately formed with hard material on the surface of the DUV PR 106 to protect DUV PR 106 .
- the hard mask layer 110 is formed on the DUV PR 106 and the width of the opening 108 in FIG. 1B can be reduced. Therefore the width of the opening 112 in FIG. IC is also narrower as the insulating layer 104 is defined by the opening 108 .
- the hard mask layer 110 swells after its formation and the width of the opening 108 , designed to be about 0.25 ⁇ m wide, can be reduce to 0.15 ⁇ m because of swelling of the hard mask layer 110 .
- This particular characteristics can improve the pattern resolution beyond the limitation of lithography.
- the etching process of the opening 112 the hard mask layer 110 and the insulating layer 104 are etched at the same time. Since the material character of the hard mask layer 110 is stronger, the etching rate is slower and the DUV PR layer 106 can be protected from overetching.
- a portion of hard mask layer 110 a a is still left on the profile of the of the hard mask layer's 110 sidewalls because the etching rate of the hard mask layer 110 is slower than the DUV PR layer 106 .
- the existence of the residual hard mask layer 110 can keep the profile of the sidewalls straight and the width of the opening 112 can be better controlled.
- the DUV PR layer 106 and the residual hard mask layer 110 a are next removed to expose the surface of the insulating layer 106 and an opening 112 with the desired width is formed. After that, a conductive layer can be deposited into the opening 112 and the subsequent process can be continued.
- the opening 112 is used as a via hole, and the conductive layer is exposed after the formation of the opening 112 . If the opening is formed for a contact hole, after forming the opening, the doped region is exactly exposed. Furthermore, the opening is for damascene and it usually exposes the conductive layer. Therefore this invention is applied in the formation of via holes, contact holes or even the openings for damascene.
- a DUV PR layer and a silylation process are applied; as a result, a hard mask layer can be formed on the DUV PR layer after exposing the DUV PR and the hard mask layer is used to protect the DUV PR from overetching. Because the DUV PR layer and the hard mask layer have different levels of etching selectivity to overcome the problem of overetching the DUV PR , the width of the contact or via can be reduced without suffering the limitation of photolithography.
Abstract
Description
- This application claims priority benefit of Taiwan application Ser. No. 87106062, filed Apr. 21, 1998, the full disclosure of which is incorporated herein by reference.
- 1. Field of the Invention
- The invention relates to a method of fabricating an opening, and more particularly to a method of fabricating an opening formed by deep ultra-violet photoresist (DUV PR).
- 2. Description of the Related Art
- Deep ultra-violet photoresist is necessary for the semiconductor process with the size of 0.25 μm or less. It can be employed in, for example, oxide layer etching. The DUV PR is exposed under a deep ultra-violet light and developed to define the oxide layer. An opening for a contact, via or damascene is then formed by developing the DUV PR. DUV PR is used to reduce the width of the opening but the material of the DUV PR is soft and not high temperature compatible. Thus erosion and reflow of the DUV PR easily occurs while etching the oxide layer which requires high ion energy. Thus, the side profile of the DUV PR isn't entirely vertical and it is difficult to precisely control the width of the opening. A commonly employed method of preventing overetching of the DUV PR is to increase the thickness of the DUV PR. However, the increment of the thickness prevents the photoresist from being properly exposed and successfully developed, because of focus of depth. Therefore increasing the thickness of the DUV PR as described above doesn't solve the problem.
- It is therefore an object of the invention to overcome the problem of erosion and reflow of the DUV PR. The width of the opening can be reduced as much as possible to follow the trend towards smaller size . The quality of the opening width can also be controlled in a stable fashion.
- To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating an opening with deep ultra-violet photoresist. An insulating layer is formed over a substrate where devices are formed thereon. A DUV PR layer with a first opening is then formed on the insulating layer. A hard mask layer is formed on the DUV PR layer and a second opening is next formed within the insulating layer by using the first opening to define the insulating layer. The hard mask is used to protect the DUV PR layer. The DUV PR layer and the hard mask are removed to expose the insulating layer and a desired second opening is thus formed.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
- FIGS.1A-1D is a cross sectional view of the formation of an opening in a preferred embodiment according to the invention.
- This invention is about a method of fabricating an opening within the insulating layer In the semiconductor process, the opening for the contact, via or damascene can be formed by this invention. The example below is made in reference to an opening for a via.
- In FIG. 1A, a
substrate 100 has device structures (not shown) and aconductive layer 102 formed on it. Theconductive layer 102 is, for example, a metal layer or polysilicon with dopant. An insulating layer 106 (or dielectric layer), such as a silicon oxide layer, is formed over thesubstrate 100. ADUV PR layer 106 with anopening 108 is then formed on the insulating layer, with theopening 108 located over a via opening formed within theinsulating layer 104 in the subsequent process. With the short wave length of deep ultra-violet light, the resolution of the light source improves and the width of theopening 108 can be narrower to follow the needs of design rule. - Next, in FIG. 2B, a
hard mask layer 110 is formed on the surface of the DUVPR 106. Thehard mask layer 110 includes a silicon layer, which is formed by silylation. If a plasma treatment is performed after silylation, the silicon layer can become an oxide layer or a nitride layer as oxygen or nitrogen is pumped into the plasma chamber. Theopening 108 within theDUV PR 110 is used to define theinsulating layer 104, and anopening 112 is then formed within theinsulating layer 104, exposing the surface of theconductive layer 102 as shown in FIG. 2C. The opening 112 can be formed by dry etching. - The material character of the DUV
PR 106 is soft, and as previously mentioned, suffers erosion and reflow by etchant as theopening 112 is formed within theinsulating layer 104. This makes it impossible to achieve a thoroughlyvertical opening 112. Thehard mask layer 110 is deliberately formed with hard material on the surface of the DUVPR 106 to protect DUVPR 106. In addition, thehard mask layer 110 is formed on the DUVPR 106 and the width of theopening 108 in FIG. 1B can be reduced. Therefore the width of theopening 112 in FIG. IC is also narrower as theinsulating layer 104 is defined by theopening 108. For example, thehard mask layer 110 swells after its formation and the width of theopening 108, designed to be about 0.25 μm wide, can be reduce to 0.15 μm because of swelling of thehard mask layer 110. This particular characteristics can improve the pattern resolution beyond the limitation of lithography. During the etching process of theopening 112, thehard mask layer 110 and theinsulating layer 104 are etched at the same time. Since the material character of thehard mask layer 110 is stronger, the etching rate is slower and theDUV PR layer 106 can be protected from overetching. After the etching process, a portion ofhard mask layer 110 a a is still left on the profile of the of the hard mask layer's 110 sidewalls because the etching rate of thehard mask layer 110 is slower than theDUV PR layer 106. The existence of the residualhard mask layer 110 can keep the profile of the sidewalls straight and the width of theopening 112 can be better controlled. - Referring to FIG. 1D, the
DUV PR layer 106 and the residualhard mask layer 110 a are next removed to expose the surface of theinsulating layer 106 and anopening 112 with the desired width is formed. After that, a conductive layer can be deposited into theopening 112 and the subsequent process can be continued. - The
opening 112 is used as a via hole, and the conductive layer is exposed after the formation of theopening 112. If the opening is formed for a contact hole, after forming the opening, the doped region is exactly exposed. Furthermore, the opening is for damascene and it usually exposes the conductive layer. Therefore this invention is applied in the formation of via holes, contact holes or even the openings for damascene. - A DUV PR layer and a silylation process are applied; as a result, a hard mask layer can be formed on the DUV PR layer after exposing the DUV PR and the hard mask layer is used to protect the DUV PR from overetching. Because the DUV PR layer and the hard mask layer have different levels of etching selectivity to overcome the problem of overetching the DUV PR , the width of the contact or via can be reduced without suffering the limitation of photolithography.
- Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims.
Claims (19)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW087106062A TW370687B (en) | 1998-04-21 | 1998-04-21 | Manufacturing method for forming an opening with deep ultra-violet photoresist |
TW87106062 | 1998-04-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010001702A1 true US20010001702A1 (en) | 2001-05-24 |
US6294314B2 US6294314B2 (en) | 2001-09-25 |
Family
ID=21629940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/076,243 Expired - Lifetime US6294314B2 (en) | 1998-04-21 | 1998-05-11 | Method of fabricating an opening with deep ultra-violet photoresist |
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US (1) | US6294314B2 (en) |
TW (1) | TW370687B (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6475904B2 (en) * | 1998-12-03 | 2002-11-05 | Advanced Micro Devices, Inc. | Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques |
JP4002704B2 (en) * | 1999-12-14 | 2007-11-07 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
US6602794B1 (en) * | 2001-03-09 | 2003-08-05 | Advanced Micro Devices, Inc. | Silylation process for forming contacts |
US6699792B1 (en) * | 2001-07-17 | 2004-03-02 | Advanced Micro Devices, Inc. | Polymer spacers for creating small geometry space and method of manufacture thereof |
US7253113B2 (en) * | 2003-11-13 | 2007-08-07 | Macronix International Co., Ltd. | Methods for using a silylation technique to reduce cell pitch in semiconductor devices |
US6979641B2 (en) * | 2004-03-19 | 2005-12-27 | Micron Technology, Inc. | Methods of forming a conductive contact through a dielectric |
KR100976647B1 (en) * | 2007-04-25 | 2010-08-18 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61151533A (en) * | 1984-12-25 | 1986-07-10 | Yokogawa Electric Corp | Formation of lift-off pattern |
US4999280A (en) * | 1989-03-17 | 1991-03-12 | International Business Machines Corporation | Spray silylation of photoresist images |
US5041362A (en) * | 1989-07-06 | 1991-08-20 | Texas Instruments Incorporated | Dry developable resist etch chemistry |
US5217851A (en) * | 1989-09-05 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Pattern forming method capable of providing an excellent pattern of high resolution power and high sensitivity |
US5550007A (en) * | 1993-05-28 | 1996-08-27 | Lucent Technologies Inc. | Surface-imaging technique for lithographic processes for device fabrication |
US5895740A (en) * | 1996-11-13 | 1999-04-20 | Vanguard International Semiconductor Corp. | Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers |
US5876903A (en) * | 1996-12-31 | 1999-03-02 | Advanced Micro Devices | Virtual hard mask for etching |
US5863707A (en) * | 1997-02-11 | 1999-01-26 | Advanced Micro Devices, Inc. | Method for producing ultra-fine interconnection features |
-
1998
- 1998-04-21 TW TW087106062A patent/TW370687B/en not_active IP Right Cessation
- 1998-05-11 US US09/076,243 patent/US6294314B2/en not_active Expired - Lifetime
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US6294314B2 (en) | 2001-09-25 |
TW370687B (en) | 1999-09-21 |
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