KR102657145B1 - 집적 회로 패키지 워크프레스 테스팅 시스템들에 대한 밸런싱된 합치력 메커니즘 - Google Patents

집적 회로 패키지 워크프레스 테스팅 시스템들에 대한 밸런싱된 합치력 메커니즘 Download PDF

Info

Publication number
KR102657145B1
KR102657145B1 KR1020207014594A KR20207014594A KR102657145B1 KR 102657145 B1 KR102657145 B1 KR 102657145B1 KR 1020207014594 A KR1020207014594 A KR 1020207014594A KR 20207014594 A KR20207014594 A KR 20207014594A KR 102657145 B1 KR102657145 B1 KR 102657145B1
Authority
KR
South Korea
Prior art keywords
pusher
chip package
pusher pin
pins
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020207014594A
Other languages
English (en)
Korean (ko)
Other versions
KR20200078560A (ko
Inventor
모센 에이치. 마디
데이비드 엠. 마호니
Original Assignee
자일링크스 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/794,479 external-priority patent/US10367279B2/en
Priority claimed from US15/802,251 external-priority patent/US10564212B2/en
Priority claimed from US15/802,253 external-priority patent/US10539610B2/en
Application filed by 자일링크스 인코포레이티드 filed Critical 자일링크스 인코포레이티드
Publication of KR20200078560A publication Critical patent/KR20200078560A/ko
Application granted granted Critical
Publication of KR102657145B1 publication Critical patent/KR102657145B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433—Sockets for IC's or transistors
    • G01R1/0441—Details
    • G01R1/0466—Details concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2865—Holding devices, e.g. chucks; Handlers or transport devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2896—Testing of IC packages; Test features related to IC packages

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
KR1020207014594A 2017-10-26 2018-10-25 집적 회로 패키지 워크프레스 테스팅 시스템들에 대한 밸런싱된 합치력 메커니즘 Active KR102657145B1 (ko)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US15/794,479 2017-10-26
US15/794,479 US10367279B2 (en) 2017-10-26 2017-10-26 Pusher pin having a non-electrically conductive portion
US15/802,251 US10564212B2 (en) 2017-11-02 2017-11-02 Integrated circuit package testing system
US15/802,251 2017-11-02
US15/802,253 US10539610B2 (en) 2017-11-02 2017-11-02 Chip package test system
US15/802,253 2017-11-02
PCT/US2018/057586 WO2019084318A1 (en) 2017-10-26 2018-10-25 BALANCED CONFORMATION FORCE MECHANISM FOR INTEGRATED CIRCUIT BOX WORK PRESS SYSTEMS

Publications (2)

Publication Number Publication Date
KR20200078560A KR20200078560A (ko) 2020-07-01
KR102657145B1 true KR102657145B1 (ko) 2024-04-11

Family

ID=64362641

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020207014594A Active KR102657145B1 (ko) 2017-10-26 2018-10-25 집적 회로 패키지 워크프레스 테스팅 시스템들에 대한 밸런싱된 합치력 메커니즘

Country Status (5)

Country Link
EP (1) EP3701273B1 (enExample)
JP (1) JP7247177B2 (enExample)
KR (1) KR102657145B1 (enExample)
CN (1) CN111316109B (enExample)
WO (1) WO2019084318A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113053774A (zh) * 2019-12-27 2021-06-29 迪科特测试科技(苏州)有限公司 探测装置
TWI817183B (zh) * 2021-08-23 2023-10-01 鴻勁精密股份有限公司 壓接機構、測試裝置及作業機
CN115754684B (zh) * 2023-01-06 2023-07-14 法特迪精密科技（苏州）有限公司 芯片老化测试台
CN116224037B (zh) * 2023-01-06 2023-10-03 法特迪精密科技（苏州）有限公司 一种芯片温度循环老化测试台上实现的芯片温度循环老化测试方法
KR20250171269A (ko) * 2024-05-28 2025-12-08 양쯔 메모리 테크놀로지스 씨오., 엘티디. 반도체 칩 패키지를 시험하기 위한 방법 및 시험 시스템

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001074815A (ja) * 1999-09-07 2001-03-23 Hitachi Telecom Technol Ltd プリント基板検査治具
US20030032326A1 (en) 2001-08-09 2003-02-13 Yamaichi Electronics Co., Ltd. IC socket
US20060068614A1 (en) 2004-09-27 2006-03-30 Wells-Cti, Llc, An Oregon Limited Liability Company Multi-site chip carrier and method
US20070096760A1 (en) 2005-10-31 2007-05-03 Edmond Cheng Method and apparatus for testing a semiconductor structure having top-side and bottom-side connections
US20070269999A1 (en) 2006-05-18 2007-11-22 Centipede Systems, Inc. Socket for an electronic device
US20090015279A1 (en) 2007-07-10 2009-01-15 Samsung Electronics Co., Ltd. Socket, and test apparatus and method using the socket
JP2012088065A (ja) 2010-10-15 2012-05-10 Hioki Ee Corp ピンボードユニットおよび基板検査装置
US20140333338A1 (en) 2011-12-07 2014-11-13 Larisys Industries Device for checking electronic cards
DE102015215634A1 (de) 2015-08-17 2017-02-23 Atx Hardware Gmbh Halter zum Niederhalten einer zu prüfenden Platine auf einen Prüfadapter in einer Prüfanordnung
US20170059611A1 (en) * 2015-09-02 2017-03-02 Oracle International Corporation Coaxial integrated circuit test socket

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025732A (en) * 1993-07-09 2000-02-15 Aehr Test Systems Reusable die carrier for burn-in and burn-in process
US5640303A (en) * 1995-10-30 1997-06-17 Precision Connector Designs, Inc. Interconnection apparatus for semiconductor/integrated circuit devices
JPH09159694A (ja) * 1995-12-08 1997-06-20 Nec Corp Ｌｓｉテストプローブ装置
JPH10221398A (ja) * 1997-01-31 1998-08-21 Aiwa Co Ltd プリント基板の検査装置
JPH11243271A (ja) * 1998-02-25 1999-09-07 Fuji Photo Film Co Ltd 基板矯正装置
JPH11242067A (ja) * 1998-02-25 1999-09-07 Fuji Photo Film Co Ltd 基板検査装置
JP2009121992A (ja) * 2007-11-15 2009-06-04 Sharp Corp 電子回路基板およびテスト装置
JP2011257239A (ja) * 2010-06-08 2011-12-22 Renesas Electronics Corp 電子装置の電気的特性検査装置及び電気的特性検査方法
US9082644B2 (en) * 2013-01-18 2015-07-14 Infineon Technologies Ag Method of manufacturing and testing a chip package
CN103399268A (zh) * 2013-07-19 2013-11-20 上海韬盛电子科技有限公司 顶针式的集成电路测试治具
KR101782600B1 (ko) * 2016-02-02 2017-10-23 (주)티에스이 반도체 패키지 테스트 장치
CN108170944B (zh) * 2017-12-26 2021-07-30 全球能源互联网研究院有限公司 一种半导体器件的压力均衡制作参数优化方法及制作方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001074815A (ja) * 1999-09-07 2001-03-23 Hitachi Telecom Technol Ltd プリント基板検査治具
US20030032326A1 (en) 2001-08-09 2003-02-13 Yamaichi Electronics Co., Ltd. IC socket
US20060068614A1 (en) 2004-09-27 2006-03-30 Wells-Cti, Llc, An Oregon Limited Liability Company Multi-site chip carrier and method
US20070096760A1 (en) 2005-10-31 2007-05-03 Edmond Cheng Method and apparatus for testing a semiconductor structure having top-side and bottom-side connections
US20070269999A1 (en) 2006-05-18 2007-11-22 Centipede Systems, Inc. Socket for an electronic device
US20090015279A1 (en) 2007-07-10 2009-01-15 Samsung Electronics Co., Ltd. Socket, and test apparatus and method using the socket
JP2012088065A (ja) 2010-10-15 2012-05-10 Hioki Ee Corp ピンボードユニットおよび基板検査装置
US20140333338A1 (en) 2011-12-07 2014-11-13 Larisys Industries Device for checking electronic cards
DE102015215634A1 (de) 2015-08-17 2017-02-23 Atx Hardware Gmbh Halter zum Niederhalten einer zu prüfenden Platine auf einen Prüfadapter in einer Prüfanordnung
US20170059611A1 (en) * 2015-09-02 2017-03-02 Oracle International Corporation Coaxial integrated circuit test socket

Also Published As

Publication number Publication date
WO2019084318A1 (en) 2019-05-02
EP3701273B1 (en) 2025-03-26
KR20200078560A (ko) 2020-07-01
JP7247177B2 (ja) 2023-03-28
CN111316109B (zh) 2023-04-07
JP2021501317A (ja) 2021-01-14
CN111316109A (zh) 2020-06-19
EP3701273A1 (en) 2020-09-02

Similar Documents

Publication Publication Date Title
US10564212B2 (en) Integrated circuit package testing system
KR102657145B1 (ko) 집적 회로 패키지 워크프레스 테스팅 시스템들에 대한 밸런싱된 합치력 메커니즘
US10539610B2 (en) Chip package test system
US10367279B2 (en) Pusher pin having a non-electrically conductive portion
US7196907B2 (en) Elasto-plastic sockets for Land or Ball Grid Array packages and subsystem assembly
US6809930B2 (en) Cooling a microchip on a circuit board
EP2051293A1 (en) Parallelism adjusting mechanism of probe card
EP0369115B1 (en) Thermal conduction module
DE10397020B4 (de) Werkstück-Einspannvorrichtung mit Temperatursteuereinheit mit Abstandshaltern zwischen Schichten, die einen Zwischenraum für thermoelektrische Module schaffen und Verfahren zum Halten eines Werkstücks
US10257952B2 (en) Side clamping BGA socket
US9791501B2 (en) Compliant thermal contact device and method
DE112023004426T5 (de) Thermokopf zur unabhängigen steuerung von zonen
JP2005055426A (ja) 電子コンポーネント試験装置及び電子コンポーネントの試験方法
EP2168144A1 (en) Subassembly that includes a power semiconductor die and a heat sink and method of forming same
US10527670B2 (en) Testing system for lid-less integrated circuit packages
JP2010534844A (ja) 電子部品、特にｉｃを保持しかつ移動する熱伝導体を有するプランジャ
US10473713B2 (en) Interposer block with retractable spring pin top cover plate
US20240356285A1 (en) Connector system for connecting processor systems and related methods
US20040159463A1 (en) Uniform force hydrostatic bolster plate
KR101922848B1 (ko) 탄성체가 설치된 프로브카드
JP2013089464A (ja) Ｉｃソケット
US6921272B2 (en) Method and apparatus for providing positive contact force in an electrical assembly
JP2004538602A (ja) ランド・グリッド・アレイ・コネクタ用の取外し可能締め付け手段
US20180358322A1 (en) Pressing solder bumps to match probe profile during wafer level testing
KR20100045034A (ko) 접속체 구조물 및 이를 갖는 기판 어셈블리

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20200521

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20211012

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20230912

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20240202

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20240408

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20240408

End annual number: 3

Start annual number: 1

PG1601 Publication of registration