KR102578576B1 - 3차원 집적 회로 - Google Patents

3차원 집적 회로 Download PDF

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KR102578576B1
KR102578576B1 KR1020207019044A KR20207019044A KR102578576B1 KR 102578576 B1 KR102578576 B1 KR 102578576B1 KR 1020207019044 A KR1020207019044 A KR 1020207019044A KR 20207019044 A KR20207019044 A KR 20207019044A KR 102578576 B1 KR102578576 B1 KR 102578576B1
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South Korea
Prior art keywords
layer
delete delete
substrate
cleaving
layers
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KR1020207019044A
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English (en)
Korean (ko)
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KR20200099156A (ko
Inventor
테오도르 이. 퐁
마이클 아이. 커런트
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실리콘 제너시스 코포레이션
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Priority claimed from US15/829,442 external-priority patent/US10049915B2/en
Priority claimed from US15/899,622 external-priority patent/US20180175008A1/en
Priority claimed from US16/057,747 external-priority patent/US10573627B2/en
Application filed by 실리콘 제너시스 코포레이션 filed Critical 실리콘 제너시스 코포레이션
Publication of KR20200099156A publication Critical patent/KR20200099156A/ko
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Publication of KR102578576B1 publication Critical patent/KR102578576B1/ko

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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
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US15/829,442 2017-12-01
US15/829,442 US10049915B2 (en) 2015-01-09 2017-12-01 Three dimensional integrated circuit
US15/899,622 US20180175008A1 (en) 2015-01-09 2018-02-20 Three dimensional integrated circuit
US15/899,622 2018-02-20
US16/057,747 US10573627B2 (en) 2015-01-09 2018-08-07 Three dimensional integrated circuit
US16/057,747 2018-08-07
PCT/US2018/063328 WO2019108945A1 (fr) 2017-12-01 2018-11-30 Circuit intégré tridimensionnel

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