EP3718134A4 - Circuit intégré tridimensionnel - Google Patents

Circuit intégré tridimensionnel Download PDF

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Publication number
EP3718134A4
EP3718134A4 EP18883845.2A EP18883845A EP3718134A4 EP 3718134 A4 EP3718134 A4 EP 3718134A4 EP 18883845 A EP18883845 A EP 18883845A EP 3718134 A4 EP3718134 A4 EP 3718134A4
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
dimensional integrated
dimensional
circuit
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18883845.2A
Other languages
German (de)
English (en)
Other versions
EP3718134A1 (fr
Inventor
Theodore E. Fong
Michael I. Current
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Genesis Corp
Original Assignee
Silicon Genesis Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/829,442 external-priority patent/US10049915B2/en
Priority claimed from US15/899,622 external-priority patent/US20180175008A1/en
Priority claimed from US16/057,747 external-priority patent/US10573627B2/en
Application filed by Silicon Genesis Corp filed Critical Silicon Genesis Corp
Publication of EP3718134A1 publication Critical patent/EP3718134A1/fr
Publication of EP3718134A4 publication Critical patent/EP3718134A4/fr
Pending legal-status Critical Current

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
EP18883845.2A 2017-12-01 2018-11-30 Circuit intégré tridimensionnel Pending EP3718134A4 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15/829,442 US10049915B2 (en) 2015-01-09 2017-12-01 Three dimensional integrated circuit
US15/899,622 US20180175008A1 (en) 2015-01-09 2018-02-20 Three dimensional integrated circuit
US16/057,747 US10573627B2 (en) 2015-01-09 2018-08-07 Three dimensional integrated circuit
PCT/US2018/063328 WO2019108945A1 (fr) 2017-12-01 2018-11-30 Circuit intégré tridimensionnel

Publications (2)

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EP3718134A1 EP3718134A1 (fr) 2020-10-07
EP3718134A4 true EP3718134A4 (fr) 2021-09-01

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JP (1) JP7328221B2 (fr)
KR (1) KR102578576B1 (fr)
CN (1) CN111684581B (fr)
TW (2) TWM588362U (fr)
WO (1) WO2019108945A1 (fr)

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JP7328221B2 (ja) 2023-08-16
TWM588362U (zh) 2019-12-21
CN111684581B (zh) 2024-08-13
EP3718134A1 (fr) 2020-10-07
KR102578576B1 (ko) 2023-09-15
TW201933585A (zh) 2019-08-16
WO2019108945A1 (fr) 2019-06-06
KR20200099156A (ko) 2020-08-21
TWI716864B (zh) 2021-01-21
JP2021506106A (ja) 2021-02-18
CN111684581A (zh) 2020-09-18

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