KR102541454B1 - 저유전막의 형성 방법, 및 반도체 소자의 형성방법 - Google Patents

저유전막의 형성 방법, 및 반도체 소자의 형성방법 Download PDF

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KR102541454B1
KR102541454B1 KR1020180048568A KR20180048568A KR102541454B1 KR 102541454 B1 KR102541454 B1 KR 102541454B1 KR 1020180048568 A KR1020180048568 A KR 1020180048568A KR 20180048568 A KR20180048568 A KR 20180048568A KR 102541454 B1 KR102541454 B1 KR 102541454B1
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supplying
forming
cycles
oxygen
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KR20190124509A (ko
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이선영
강민재
김세연
김태원
탁용석
김선정
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삼성전자주식회사
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Priority to KR1020180048568A priority Critical patent/KR102541454B1/ko
Priority to US16/217,339 priority patent/US10861695B2/en
Priority to SG10201903205R priority patent/SG10201903205RA/en
Priority to CN201910292773.4A priority patent/CN110416061B/zh
Priority to JP2019078428A priority patent/JP7256675B2/ja
Priority to EP19171041.7A priority patent/EP3561860A1/en
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    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6927—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
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US16/217,339 US10861695B2 (en) 2018-04-26 2018-12-12 Method of forming a low-k layer and method of forming a semiconductor device
SG10201903205R SG10201903205RA (en) 2018-04-26 2019-04-10 Method of forming a low-k layer and method of forming a semiconductor device
CN201910292773.4A CN110416061B (zh) 2018-04-26 2019-04-12 形成低k层的方法和形成半导体装置的方法
JP2019078428A JP7256675B2 (ja) 2018-04-26 2019-04-17 低誘電膜の形成方法及び半導体素子の形成方法
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