KR102505236B1 - 백사이드 반도체 성장 - Google Patents

백사이드 반도체 성장 Download PDF

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KR102505236B1
KR102505236B1 KR1020197003917A KR20197003917A KR102505236B1 KR 102505236 B1 KR102505236 B1 KR 102505236B1 KR 1020197003917 A KR1020197003917 A KR 1020197003917A KR 20197003917 A KR20197003917 A KR 20197003917A KR 102505236 B1 KR102505236 B1 KR 102505236B1
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backside
source
drain region
transistor
circuit structure
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KR20190036533A (ko
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시난 고크테펠리
리차드 햄몬드
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퀄컴 인코포레이티드
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    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82Heterojunctions
    • H10D62/822Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
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    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/005Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
    • H04B1/0053Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band
    • H04B1/006Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band using switches for selecting the desired band
    • HELECTRICITY
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    • H04B1/38Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
KR1020197003917A 2016-08-11 2017-07-12 백사이드 반도체 성장 Active KR102505236B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/234,889 2016-08-11
US15/234,889 US9780210B1 (en) 2016-08-11 2016-08-11 Backside semiconductor growth
PCT/US2017/041755 WO2018031175A1 (en) 2016-08-11 2017-07-12 Backside semiconductor growth

Publications (2)

Publication Number Publication Date
KR20190036533A KR20190036533A (ko) 2019-04-04
KR102505236B1 true KR102505236B1 (ko) 2023-03-02

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Country Link
US (1) US9780210B1 (https=)
EP (1) EP3497715B8 (https=)
JP (1) JP7158373B2 (https=)
KR (1) KR102505236B1 (https=)
CN (1) CN109643691B (https=)
BR (1) BR112019002343B1 (https=)
CA (1) CA3030289C (https=)
WO (1) WO2018031175A1 (https=)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017052562A1 (en) 2015-09-24 2017-03-30 Intel Corporation Methods of forming backside self-aligned vias and structures formed thereby
EP3440705A4 (en) 2016-04-01 2019-11-13 INTEL Corporation TRANSISTOR CELLS WITH A DEEP CONTACT WITH CLADDING OF DIELECTRIC MATERIAL
US9847293B1 (en) * 2016-08-18 2017-12-19 Qualcomm Incorporated Utilization of backside silicidation to form dual side contacted capacitor
CN109643742B (zh) 2016-08-26 2024-09-27 英特尔公司 集成电路器件结构和双侧制造技术
US10431664B2 (en) * 2017-06-30 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and methods thereof
DE102018106266B4 (de) 2017-06-30 2024-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und verfahren zu ihrer herstellung
US10439565B2 (en) * 2017-09-27 2019-10-08 Qualcomm Incorporated Low parasitic capacitance low noise amplifier
KR102019354B1 (ko) 2017-11-03 2019-09-09 삼성전자주식회사 안테나 모듈
WO2019132863A1 (en) 2017-12-26 2019-07-04 Intel Corporation Stacked transistors with contact last
WO2019172879A1 (en) 2018-03-05 2019-09-12 Intel Corporation Metallization structures for stacked device connectivity and their methods of fabrication
US10580903B2 (en) 2018-03-13 2020-03-03 Psemi Corporation Semiconductor-on-insulator transistor with improved breakdown characteristics
CN110504240B (zh) * 2018-05-16 2021-08-13 联华电子股份有限公司 半导体元件及其制造方法
US20190371891A1 (en) * 2018-06-01 2019-12-05 Qualcomm Incorporated Bulk layer transfer based switch with backside silicidation
US10680086B2 (en) * 2018-06-18 2020-06-09 Qualcomm Incorporated Radio frequency silicon-on-insulator integrated heterojunction bipolar transistor
US10658386B2 (en) 2018-07-19 2020-05-19 Psemi Corporation Thermal extraction of single layer transfer integrated circuits
US10672806B2 (en) 2018-07-19 2020-06-02 Psemi Corporation High-Q integrated circuit inductor structure and methods
US10573674B2 (en) 2018-07-19 2020-02-25 Psemi Corporation SLT integrated circuit capacitor structure and methods
TWI716748B (zh) * 2018-10-11 2021-01-21 世界先進積體電路股份有限公司 半導體裝置及其製造方法
CN111092086B (zh) * 2018-10-24 2022-04-19 世界先进积体电路股份有限公司 半导体装置及其制造方法
US11688780B2 (en) 2019-03-22 2023-06-27 Intel Corporation Deep source and drain for transistor structures with back-side contact metallization
US11476363B2 (en) * 2019-04-10 2022-10-18 United Microelectronics Corp. Semiconductor device and method of fabricating the same
CN111816710A (zh) * 2019-04-10 2020-10-23 联华电子股份有限公司 半导体装置
US11296023B2 (en) * 2019-04-10 2022-04-05 United Microelectronics Corp. Semiconductor device and method of fabricating the same
KR102801648B1 (ko) * 2019-05-21 2025-05-02 삼성전자주식회사 반도체 소자
US10777636B1 (en) 2019-06-12 2020-09-15 Psemi Corporation High density IC capacitor structure
US11004972B2 (en) * 2019-06-12 2021-05-11 Globalfoundries Singapore Pte. Ltd. Semiconductor device having conducting member for electrically coupling gate structure to underlying substrate of SOI structure
KR102904447B1 (ko) * 2019-07-23 2025-12-29 삼성전자주식회사 반도체 장치
US11658220B2 (en) 2020-04-24 2023-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Drain side recess for back-side power rail device
TWI787787B (zh) 2020-04-24 2022-12-21 台灣積體電路製造股份有限公司 半導體電晶體裝置及形成半導體電晶體裝置的方法
DE102021101178B4 (de) * 2020-04-29 2024-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte-schaltkreis-struktur mit rückseitiger dielektrischer schicht mit luftspalt sowie verfahren zu deren herstellung
CN114914292B (zh) * 2020-05-11 2026-02-27 北京华碳元芯电子科技有限责任公司 一种晶体管
DE102020122823B4 (de) 2020-05-12 2022-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtungen mit entkopplungskondensatoren
DE102020131611B4 (de) 2020-05-28 2025-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit luftspalten und verfahren zu deren herstellung
US11862561B2 (en) * 2020-05-28 2024-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with backside routing and method of forming same
US11563095B2 (en) 2020-05-29 2023-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide-sandwiched source/drain region and method of fabricating same
DE102021103791A1 (de) * 2020-05-29 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Silizid-belegter source/drain-bereich und dessen herstellungsverfahren
US11626494B2 (en) 2020-06-17 2023-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial backside contact
US11532713B2 (en) 2020-06-25 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain contacts and methods of forming same
US11557510B2 (en) 2020-07-30 2023-01-17 Taiwan Semiconductor Manufacturing Co., Ltd. Spacers for semiconductor devices including backside power rails
US11456209B2 (en) 2020-07-31 2022-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Spacers for semiconductor devices including a backside power rails
US11482594B2 (en) 2020-08-27 2022-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with backside power rail and method thereof
US11588050B2 (en) * 2020-08-31 2023-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Backside contact
US11437379B2 (en) * 2020-09-18 2022-09-06 Qualcomm Incorporated Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits
US12165973B2 (en) * 2020-09-30 2024-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with backside power rail and method for forming the same
US12218664B2 (en) 2020-10-21 2025-02-04 Arm Limited Backside power supply techniques
US11658119B2 (en) * 2020-10-27 2023-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Backside signal interconnection
US11967551B2 (en) * 2021-04-07 2024-04-23 Arm Limited Standard cell architecture
US12593459B2 (en) * 2021-04-28 2026-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Backside memory integration
US12568648B2 (en) 2021-05-05 2026-03-03 Taiwan Semiconductor Manufacturing Co., Ltd. Backside source/drain contacts and methods of forming the same
CN115376994B (zh) * 2021-05-19 2025-10-21 邱志威 晶体管下具有电源连接结构的半导体结构及其制造方法
US12224286B2 (en) 2021-09-22 2025-02-11 Qualcomm Incorporated Symmetric dual-sided MOS IC
US11935927B2 (en) * 2021-11-10 2024-03-19 Globalfoundries U.S. Inc. Bipolar transistor with collector contact
US12604481B2 (en) 2021-12-21 2026-04-14 Intel Corporation IC's with multple levels of embedded memory
US20240373654A1 (en) * 2023-05-05 2024-11-07 International Business Machines Corporation Hybrid memory on front and backside of a wafer
US20240429166A1 (en) * 2023-06-23 2024-12-26 International Business Machines Corporation Trench isolation structures for backside contacts
US20260047423A1 (en) * 2024-08-08 2026-02-12 Nxp Usa, Inc. Semiconductor circuit with back-side partial-substrate power rails

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080206977A1 (en) 2007-02-22 2008-08-28 Frank David J Methods of forming wiring to transistor and related transistor
US20130134527A1 (en) 2010-11-11 2013-05-30 International Business Machines Corporation Structure and method to fabricate a body contact
US20150091092A1 (en) 2013-10-02 2015-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dynamic Threshold MOS and Methods of Forming the Same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0483348A (ja) * 1990-07-26 1992-03-17 Fujitsu Ltd 半導体装置及びその製造方法
JP3092761B2 (ja) * 1991-12-02 2000-09-25 キヤノン株式会社 画像表示装置及びその製造方法
TW473914B (en) * 2000-01-12 2002-01-21 Ibm Buried metal body contact structure and method for fabricating SOI MOSFET devices
JP3764401B2 (ja) * 2002-04-18 2006-04-05 株式会社東芝 半導体装置の製造方法
DE102004033149B4 (de) * 2004-07-08 2006-09-28 Infineon Technologies Ag Verfahren zum Herstellen eines Doppel-Gate-Transistors, einer Speicherzelle, eines Vertikaltransistors sowie vergrabenen Wort- bzw. Bitleitungen jeweils unter Verwendung einer vergrabenen Ätzstoppschicht
JP4175650B2 (ja) * 2004-08-26 2008-11-05 シャープ株式会社 半導体装置の製造方法
CN100557822C (zh) * 2004-12-28 2009-11-04 Nxp股份有限公司 半导体器件制造方法及半导体器件
US7816231B2 (en) 2006-08-29 2010-10-19 International Business Machines Corporation Device structures including backside contacts, and methods for forming same
JP2008252068A (ja) * 2007-03-08 2008-10-16 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP5322408B2 (ja) * 2007-07-17 2013-10-23 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
US7897468B1 (en) * 2009-09-10 2011-03-01 International Business Machines Corporation Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island
US8373228B2 (en) * 2010-01-14 2013-02-12 GlobalFoundries, Inc. Semiconductor transistor device structure with back side source/drain contact plugs, and related manufacturing method
US8716091B2 (en) 2010-03-30 2014-05-06 International Business Machines Corporation Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain
US8318574B2 (en) 2010-07-30 2012-11-27 International Business Machines Corporation SOI trench DRAM structure with backside strap
US8772874B2 (en) * 2011-08-24 2014-07-08 International Business Machines Corporation MOSFET including asymmetric source and drain regions
US8895379B2 (en) * 2012-01-06 2014-11-25 International Business Machines Corporation Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same
US9219129B2 (en) * 2012-05-10 2015-12-22 International Business Machines Corporation Inverted thin channel mosfet with self-aligned expanded source/drain
US9023688B1 (en) * 2013-06-09 2015-05-05 Monolithic 3D Inc. Method of processing a semiconductor device
CN104241357A (zh) 2013-06-18 2014-12-24 中芯国际集成电路制造(上海)有限公司 一种晶体管、集成电路以及集成电路的制造方法
US9209305B1 (en) * 2014-06-06 2015-12-08 Stmicroelectronics, Inc. Backside source-drain contact for integrated circuit transistor devices and method of making same
CN107924949A (zh) * 2015-09-27 2018-04-17 英特尔公司 与磁感应器集成的晶体管的两侧上的金属

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080206977A1 (en) 2007-02-22 2008-08-28 Frank David J Methods of forming wiring to transistor and related transistor
US20130134527A1 (en) 2010-11-11 2013-05-30 International Business Machines Corporation Structure and method to fabricate a body contact
US20150091092A1 (en) 2013-10-02 2015-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dynamic Threshold MOS and Methods of Forming the Same

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