KR102387336B1 - 전자 부품 - Google Patents

전자 부품 Download PDF

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Publication number
KR102387336B1
KR102387336B1 KR1020167031733A KR20167031733A KR102387336B1 KR 102387336 B1 KR102387336 B1 KR 102387336B1 KR 1020167031733 A KR1020167031733 A KR 1020167031733A KR 20167031733 A KR20167031733 A KR 20167031733A KR 102387336 B1 KR102387336 B1 KR 102387336B1
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South Korea
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solder layer
layer
solder
region
metal material
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KR1020167031733A
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English (en)
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KR20170040119A (ko
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요시마로 후지이
히로시 오구리
아키라 사카모토
도모야 다구치
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하마마츠 포토닉스 가부시키가이샤
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Publication of KR20170040119A publication Critical patent/KR20170040119A/ko
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Abstract

전자 부품(1A)은 기재(10)와, 복수의 도전성 금속 재료층(21, 22, 23)의 적층체(20)와, Au－Sn 합금 땜납으로 이루어지는 땜납층(30)을 구비하고 있다. 적층체(20)는 기재(10)상에 배치되어 있다. 땜납층(30)은 적층체(20)상에 배치되어 있다. 적층체(20)는 최외층을 구성하는 도전성 금속 재료층(23)으로서, Au로 이루어지는 표면층을 가지고 있다. 표면층은 땜납층(30)이 배치되는 땜납층 배치 영역(23a)과, 땜납층(30)이 배치되지 않는 땜납층 비배치 영역(23b)을 포함하고 있다. 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)은, 공간적으로 떨어져 있다.

Description

전자 부품{ELECTRONIC COMPONENT}
본 발명은 전자 부품에 관한 것이다.
포토 다이오드와, 포토 다이오드의 상면(上面)의 수광부 이외의 부위에 배치되어 있는 단자와, 단자에 배치되어 있는 범프(bump)를 구비한 전자 부품이 알려져 있다(예를 들어, 특허 문헌 1 참조). 이 전자 부품에는, 다른 전자 부품으로서, IC 칩이 실장된다.
특허 문헌 1 : 일본 특개 2000－307133호 공보
본 발명의 일 양태는 Au－Sn 합금 땜납(solder)을 이용하여 다른 전자 부품을 실장하는 경우에도, 당해 다른 전자 부품의 실장을 적절히 행하는 것이 가능한 전자 부품을 제공하는 것을 목적으로 한다.
본 발명의 일 양태에 따른 전자 부품은 기재(基材)와, 기재상에 배치되어 있는, 복수의 도전성 금속 재료층의 적층체와, 적층체상에 배치되어 있는 Au－Sn 합금 땜납으로 이루어지는 땜납층(solder layer)을 구비하고 있다. 적층체는 최외층(最外層)을 구성하는 도전성 금속 재료층으로서, Au로 이루어지는 표면층을 가지고 있다. 표면층은 땜납층이 배치되는 땜납층 배치 영역과, 땜납층이 배치되지 않는 땜납층 비배치 영역을 포함하고 있다. 땜납층 배치 영역과 땜납층 비배치 영역은, 공간적으로 떨어져 있다.
본 양태에 따른 전자 부품에서는, 적층체의 최외층을 구성하는 Au로 이루어지는 표면층이, 땜납층 배치 영역과 땜납층 비배치 영역을 포함하고, 땜납층 배치 영역과 땜납층 비배치 영역은 공간적으로 떨어져 있다. 상기 일 양태에 따른 전자 부품에 다른 전자 부품을 실장할 때, 적층체상에 배치되어 있는 땜납층(Au－Sn 합금 땜납)은 용융(溶融)한다. 용융한 Au－Sn 합금 땜납이 땜납층 배치 영역에서 땜납층 비배치 영역으로 유출되는 것은, 억제된다.
땜납층과 표면층의 열이력(熱履歷)에 의해, 표면층의 Au가 땜납층으로 확산되어, Au－Sn 합금 땜납의 조성이 변화하는 경우가 있다. Au－Sn 합금 땜납의 조성이 변화했을 경우, Au－Sn 합금 땜납의 융점에 스캐터(scatter)가 생기거나, 다른 전자 부품의 접합 상태가 불균일하게 되거나 할 우려가 있다. 상술한 것처럼, 땜납층 배치 영역과 땜납층 비배치 영역은 공간적으로 떨어져 있으므로, 표면층의 Au가 땜납층으로 확산하는 경우에도, 땜납층 비배치 영역의 Au는 땜납층으로 확산되는 경우는 없다. 표면층으로부터의 Au의 확산량이 억제되기 때문에, Au－Sn 합금 땜납의 조성의 변화가 억제된다.
이상으로부터, 본 양태에 의하면, Au－Sn 합금 땜납을 이용하여 다른 전자 부품을 실장하는 경우에도, 당해 다른 전자 부품의 실장을 적절히 행할 수 있다.
땜납층 배치 영역은 땜납층 비배치 영역에 둘러싸이도록, 땜납층 비배치 영역의 내측에 위치함과 아울러, 그 둘레 전체에 있어서 땜납층 비배치 영역과 공간적으로 떨어져 있어도 된다. 이 경우, 용융한 Au－Sn 합금 땜납이 땜납층 배치 영역에서 땜납층 비배치 영역으로 유출되는 것을 보다 한층 확실히 억제할 수 있다. 땜납층 배치 영역으로부터의 Au의 확산량이 보다 한층 억제되기 때문에, Au－Sn 합금 땜납의 조성의 변화를 확실히 억제할 수 있다.
땜납층 배치 영역과 땜납층 비배치 영역은, 표면층에 형성된 슬릿에 의해 공간적으로 떨어져 있어도 된다. 이 경우, 땜납층 배치 영역과 땜납층 비배치 영역이 공간적으로 떨어져 있는 구성을 간이하게 실현할 수 있다.
땜납층은 Pt로 이루어지는 배리어(barrier)층을 매개로 하여, 적층체상에 배치되어 있어도 된다. 이 경우, 땜납층 배치 영역으로부터의 Au의 확산이 방지되기 때문에, Au－Sn 합금 땜납의 조성의 변화를 보다 한층 확실히 억제할 수 있다.
본 발명의 상기 일 양태에 의하면, Au－Sn 합금 땜납을 이용하여 다른 전자 부품을 실장하는 경우에도, 당해 다른 전자 부품의 실장을 적절히 행하는 것이 가능한 전자 부품을 제공할 수 있다.
도 1은 일 실시 형태에 따른 전자 부품을 나타내는 평면도이다.
도 2는 도 1에 도시된 II－II선을 따른 단면 구성을 설명하기 위한 도면이다.
도 3은 본 실시 형태의 변형예에 따른 전자 부품의 단면 구성을 설명하기 위한 도면이다.
도 4는 땜납층을 형성하는 과정을 설명하기 위한 도면이다.
도 5는 땜납층 배치 영역과 땜납층 비배치 영역이 공간적으로 떨어져 있지 않은 전자 부품의 단면 구성을 설명하기 위한 도면이다.
도 6은 본 실시 형태의 다른 변형예에 따른 전자 부품을 나타내는 평면도이다.
도 7은 본 실시 형태의 다른 변형예에 따른 전자 부품의 단면 구성을 설명하기 위한 도면이다.
도 8은 본 실시 형태의 다른 변형예에 따른 전자 부품을 나타내는 평면도이다.
이하, 도면을 참조하면서, 본 발명의 실시 형태에 대해 상세하게 설명한다. 또한, 설명에 있어서, 동일 요소 또는 동일 기능을 가지는 요소에는, 동일 부호를 이용하는 것으로 하고, 중복하는 설명은 생략한다.
도 1 및 도 2를 참조하여, 본 실시 형태에 따른 전자 부품(1A)의 구성을 설명한다. 도 1은 본 실시 형태에 따른 전자 부품의 평면도이다. 도 2는 도 1에 도시된 II－II선을 따른 단면 구성을 설명하기 위한 도면이다.
전자 부품(1A)은 기재(10), 적층체(20), 및 땜납층(30)을 구비하고 있다. 전자 부품(1A)은, 예를 들어, 다른 전자 부품(3)이 실장되는 서브 마운트 기판으로서 기능한다. 다른 전자 부품(3)은, 예를 들어, 레이저 다이오드 등이다. 실장에는, 전기적 또한 물리적으로 접속하는 것만이 아니라, 물리적으로만 접속하는 것도 포함된다.
기재(10)는 반도체 기판(11)을 포함하고 있다. 반도체 기판(11)은 서로 대향(對向)하는 한 쌍의 주면(主面)(11a, 11b)과, 측면(11c)을 가지는, 제1 도전형(예를 들어, N형)의 실리콘 기판이다. 측면(11c)은 한 쌍의 주면(11a, 11b) 사이를 연결하도록 한 쌍의 주면(11a, 11b)의 대향 방향으로 연장되어 있다. 본 실시 형태에서는, 반도체 기판(11)은 도 1에 도시되는 것처럼, 평면에서 볼 때 사각형 형상을 나타내고 있고, 네 개의 측면(11c)을 가진다.
반도체 기판(11)은 주면(11a)측에 위치하는 제2 도전형(예를 들어, P형)의 제1 반도체 영역(13)을 가지고 있다. 제1 반도체 영역(13)은 제2 도전형의 불순물(붕소 등)이 첨가된 영역이다. 제1 반도체 영역(13)은 반도체 기판(11)보다도 불순물 농도가 높다. 제1 반도체 영역(13)은, 예를 들어, 이온 주입법 또는 확산법에 의해, 제2 도전형의 불순물을 주면(11a)측으로부터 반도체 기판(11)에 첨가함으로써 형성된다.
기재(10)에서는, 반도체 기판(11)과 제1 반도체 영역(13)으로 PN 접합이 형성되어 있다. 즉, 기재(10)는 주면(11a)이 광입사면인 표면 입사형의 포토 다이오드이다. 제1 반도체 영역(13)은 반도체 기판(11)과 광 감응 영역을 구성하고 있다. 다른 전자 부품(3)으로서 레이저 다이오드가 전자 부품(1A)에 실장되는 경우, 상기 포토 다이오드는 레이저 다이오드의 출력을 모니터한다.
기재(10)는 패시베이션(passivation)막(15)을 포함하고 있다. 패시베이션막(15)은, 반도체 기판(11)의 주면(11a)상에 배치되어 있다. 패시베이션막(15)에는, 제1 반도체 영역(13)에 대응하는 위치에 개구(15a)가 형성되어 있다. 제1 반도체 영역(13)(광 감응 영역)에는, 패시베이션막(15)에 형성된 개구(15a)를 통과하여, 광이 입사한다. 패시베이션막(15)은, 예를 들어 SiN으로 이루어진다. 패시베이션막(15)은, 예를 들어 CVD(Chemical Vapor Deposition)법에 의해 형성된다. 본 실시 형태에서는, 상기 포토 다이오드에 접속되는 캐소드 전극(패드) 및 애노드 전극(패드)의 도시를 생략하고 있다.
적층체(20)는 기재(10)(패시베이션막(15))상에 배치되어 있다. 상세하게는, 적층체(20)는 패시베이션막(15)에 있어서의, 개구(15a)가 형성되어 있지 않은 영역상에 배치되어 있다. 적층체(20)는 복수의 도전성 금속 재료층으로 이루어진다. 본 실시 형태에서는, 적층체(20)는 3층의 도전성 금속 재료층(21, 22, 23)으로 이루어진다. 각 도전성 금속 재료층(21, 22, 23)은 도전성 금속재료로 이루어지는 층이다. 3층의 도전성 금속 재료층(21, 22, 23)은 기재(10)측으로부터, 도전성 금속 재료층(21), 도전성 금속 재료층(22), 도전성 금속 재료층(23)의 순으로 적층되어 있다. 각 도전성 금속 재료층(21, 22, 23)은, 예를 들어 진공 증착법 또는 스패터링( spattering)법에 의해 형성된다.
도전성 금속 재료층(21)은 기재(10)(패시베이션막(15))와의 접촉층을 구성하고 있다. 도전성 금속 재료층(21)은 기재(10)(패시베이션막(15))와의 밀착성을 높인다. 도전성 금속 재료층(21)은, 예를 들어 Ti로 이루어진다. 도전성 금속 재료층(21)의 두께는, 예를 들어 0.1~0.2㎛이다. 도전성 금속 재료층(21)은 Ti 이외에, Cr 등으로 이루어져 있어도 된다.
도전성 금속 재료층(22)은 중간의 배리어층을 구성하고 있다. 도전성 금속 재료층(22)은 다른 도전성 금속 재료층(21, 23)으로부터 금속재료(금속 원자)가 확산하는 것을 방지한다. 도전성 금속 재료층(22)은, 예를 들어 Pt로 이루어진다. 도전성 금속 재료층(22)의 두께는, 예를 들어 0.2~0.3㎛이다.
도전성 금속 재료층(23)은 적층체(20)의 최외층을 구성한다. 즉, 도전성 금속 재료층(23)은 표면층을 구성하고 있다. 도전성 금속 재료층(23)은, 예를 들어 Au로 이루어진다. 도전성 금속 재료층(23)의 두께는, 예를 들어 0.1~0.5㎛이다.
도전성 금속 재료층(23)은 땜납층(30)이 배치되는 땜납층 배치 영역(23a)과, 땜납층(30)이 배치되지 않는 땜납층 비배치 영역(23b)을 포함하고 있다. 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)은, 도전성 금속 재료층(22)상에 있어서, 공간적으로 떨어져 있다. 즉, 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)이 공간적으로 떨어져 있는 영역에서는, 도전성 금속 재료층(22)이 노출되어 있다.
본 실시 형태에서는, 땜납층 배치 영역(23a)은 땜납층 비배치 영역(23b)에 둘러싸이도록, 땜납층 비배치 영역(23b)의 내측에 위치함과 아울러, 그 둘레 전체에 있어서 땜납층 비배치 영역(23b)과 공간적으로 떨어져 있다. 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)은, 도전성 금속 재료층(23)에 형성된 슬릿(23c)에 의해 공간적으로 떨어져 있다.
땜납층(30)은 Au－Sn 합금 땜납으로 이루어지고, 적층체(20)(도전성 금속 재료층(23)의 땜납층 배치 영역(23a)) 상에 배치되어 있다. 땜납층(30)은 도전성 금속 재료층(23)(땜납층 배치 영역(23a))에 접해 있다. 땜납층(30)은, 예를 들어 포토레지스트(photoresist)(네거티브형 포토레지스트)를 이용한 리프트 오프법에 의해 형성된다. 땜납층(30)의 두께는, 예를 들어 2.0~5.0㎛이다.
이상과 같이, 본 실시 형태에서는, Au로 이루어지는 도전성 금속 재료층(23)이, 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)을 포함하고, 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)은 공간적으로 떨어져 있다. 전자 부품(1A)에 다른 전자 부품(3)을 실장할 때, 적층체(20)상에 배치되어 있는 땜납층(30)(Au－Sn 합금 땜납)은 용융한다. 용융한 Au－Sn 합금 땜납이 땜납층 배치 영역(23a)에서 땜납층 비배치 영역(23b)으로 유출되는 것은, 억제된다.
전자 부품(1A)의 제조 과정에 있어서의 땜납층(30)과 도전성 금속 재료층(23)의 열이력에 의해, 도전성 금속 재료층(23)의 Au가 땜납층(30)으로 확산되어, Au－Sn 합금 땜납의 조성이 변화하는 경우가 있다. Au－Sn 합금 땜납의 조성이 변화했을 경우, Au－Sn 합금 땜납의 융점에 스캐터가 생기거나, 다른 전자 부품(3)의 접합 상태가 불균일하게 되거나 할 우려가 있다.
본 실시 형태에서는, 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)은 공간적으로 떨어져 있으므로, 도전성 금속 재료층(23)의 Au가 땜납층(30)으로 확산되는 경우에도, 땜납층 비배치 영역(23b)의 Au는 땜납층(30)으로 확산되는 경우는 없다. 도전성 금속 재료층(23)으로부터의 Au의 확산량이 억제되기 때문에, Au－Sn 합금 땜납의 조성의 변화가 억제된다.
이들 결과, 전자 부품(1A)에 의하면, Au－Sn 합금 땜납을 이용하여 다른 전자 부품(3)을 실장하는 경우에도, 다른 전자 부품(3)의 실장을 적절히 행할 수 있다.
본 실시 형태에서는, 땜납층 배치 영역(23a)은 땜납층 비배치 영역(23b)에 둘러싸이도록, 땜납층 비배치 영역(23b)의 내측에 위치함과 아울러, 그 둘레 전체에 있어서 땜납층 비배치 영역(23b)과 공간적으로 떨어져 있다. 이것에 의해, 용융한 Au－Sn 합금 땜납이 땜납층 배치 영역(23a)에서 땜납층 비배치 영역(23b)으로 유출되는 것을 보다 한층 확실히 억제할 수 있다. 땜납층 배치 영역(23a)으로부터의 Au의 확산량이 보다 한층 억제되기 때문에, Au－Sn 합금 땜납의 조성의 변화를 확실히 억제할 수 있다.
본 실시 형태에서는, 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)은, 도전성 금속 재료층(23)에 형성된 슬릿에 의해 공간적으로 떨어져 있다. 이것에 의해, 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)이 공간적으로 떨어져 있는 구성을 간이하게 실현할 수 있다.
다음에, 도 3을 참조하여, 본 실시 형태의 변형예에 따른 전자 부품(1B)의 구성을 설명한다. 도 3은 본 실시 형태의 변형예에 따른 전자 부품의 단면 구성을 설명하기 위한 도면이다.
전자 부품(1B)은 기재(10), 적층체(20), 땜납층(30) 및 배리어층(40)을 구비하고 있다. 전자 부품(1B)도, 전자 부품(1A)과 마찬가지로, 예를 들어, 다른 전자 부품(3)이 실장되는 서브 마운트 기판으로서 기능한다.
배리어층(40)은 적층체(20)와 땜납층(30)의 사이에 배치되어 있다. 배리어층(40)은 적층체(20)(도전성 금속 재료층(23))에 접함과 아울러, 땜납층(30)에 접해 있다. 즉, 땜납층(30)은 배리어층(40)을 매개로 하여, 적층체(20)상에 배치되어 있다. 배리어층(40)은 Pt로 이루어진다. 배리어층(40)은, 예를 들어, 리프트 오프법에 의해 땜납층(30)과 함께 형성된다. 배리어층(40)의 두께는, 예를 들어 0.2~0.3㎛이다.
본 변형예에서는, 배리어층(40)에 의해, 도전성 금속 재료층(23)(땜납층 배치 영역(23a))으로부터의 Au의 확산이 방지된다. 따라서 전자 부품(1B)에 있어서, Au－Sn 합금 땜납의 조성의 변화를 보다 한층 확실히 억제할 수 있다.
배리어층(40)이 적층체(20)와 땜납층(30)의 사이에 배치되어 있는 경우, 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)이 공간적으로 떨어져 있지 않더라도, 땜납층 배치 영역(23a)으로부터 땜납층 비배치 영역(23b)으로의 용융한 Au－Sn 합금 땜납의 유출이 억제되는 것이 기대된다. 그렇지만, 이하의 사상에 의해, 배리어층(40)이 존재하고 있는 경우에도, 상술한 용융한 Au－Sn 합금 땜납의 유출은 억제되기 어렵다.
땜납층(30)이 상술한 리프트 오프법에 의해 형성되어 있는 경우, 포토레지스트(50)의 형상에 기인하여, 도 4 및 도 5에 도시되는 것처럼, 땜납층(30)이 배리어층(40)보다도 넓게 형성된다. 즉, 땜납층(30)은 배리어층(40)을 덮음과 아울러 적층체(20)(도전성 금속 재료층(23))에 접하도록 형성된다. 땜납층(30)의 두께는, 일반적으로, 배리어층(40)의 두께보다도 크다. 이 때문에, 땜납층(30)은 당해 땜납층(30)에 평행한 방향으로 퍼지기 쉽고, 땜납층(30)이 배리어층(40)보다도 보다 한층 넓게 형성되어 버린다. 땜납층(30)이 도전성 금속 재료층(23)에 접해 있으면, 용융한 Au－Sn 합금 땜납은 도전성 금속 재료층(23)상을 적시면서 퍼질 우려가 있다. 이 때문에, 땜납층 배치 영역(23a)에서 땜납층 비배치 영역(23b)으로 유출되어 버린다.
본 변형예에서는 전자 부품(1A)과 마찬가지로, 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)은 공간적으로 떨어져 있다. 이것에 의해, 용융한 Au－Sn 합금 땜납의 땜납층 배치 영역(23a)에서 땜납층 비배치 영역(23b)으로의 유출은, 확실히 억제된다.
이상, 본 발명의 실시 형태에 대해 설명해 왔지만, 본 발명은 반드시 상술한 실시 형태로 한정되는 것이 아니고, 그 요지를 일탈하지 않는 범위에서 다양한 변경이 가능하다.
기재(10)는 표면 입사형의 포토 다이오드로 한정되지 않는다. 기재(10)는 도 6 및 도 7에 도시되는 것처럼, 적어도 어느 하나의 측면(11c)이 광입사면인 측면 입사형의 포토 다이오드여도 좋다. 도 6 및 도 7에 도시된 전자 부품(1A)에서는, 패시베이션막(15)으로부터 노출되도록, 캐소드 전극(패드)(61)과, 애노드 전극(패드)(63)이 배치되어 있다. 도 6은 본 실시 형태의 다른 변형예에 따른 전자 부품을 나타내는 평면도이다. 도 7은 본 실시 형태의 다른 변형예에 따른 전자 부품의 단면 구성을 설명하기 위한 도면이다.
땜납층 배치 영역(23a)은 땜납층 비배치 영역(23b)에 둘러싸이도록, 땜납층 비배치 영역(23b)의 내측에 위치함과 아울러, 그 둘레 전체에 있어서 땜납층 비배치 영역(23b)과 공간적으로 떨어져 있을 필요는 없다. 예를 들어, 땜납층 배치 영역(23a)과 땜납층 비배치 영역(23b)은, 도 8에 도시되는 것처럼, 직선 모양의 슬릿(23c)으로 분할되도록 공간적으로 떨어져 있어도 된다.
적층체(20)는 3층의 도전성 금속 재료층(21, 22, 23)으로 이루어질 필요는 없다. 적층체(20)는 2층의 도전성 금속 재료층으로 이루어져 있어도 되고, 또, 4층 이상의 도전성 금속 재료층으로 이루어져 있어도 된다. 이들 경우에도, 적층체(20)에 있어서의 최외층을 구성하는 도전성 금속 재료층, 즉 표면층이 Au로 이루어져 있으면 된다.
기재(10)는 포토 다이오드가 아니어도 되고, 또, 기재(10)는 반도체 기판(11)을 포함하고 있을 필요는 없다. 기재(10)는 반도체 기판(11) 대신에, 예를 들어 세라믹 기판 또는 유리 기판 등을 포함하고 있어도 된다. 세라믹 기판에는, 질화 알루미늄(AlN) 기판 또는 알루미나(Al2O3) 기판 등이 이용된다.
전자 부품(1A, 1B)에 실장되는 다른 전자 부품(3)은, 레이저 다이오드일 필요는 없다. 다른 전자 부품(3)은, 예를 들어 수광 소자, 발광 소자, 반도체 패키지, 회로 기판, 능동 부품, 또는 수동 부품이어도 좋다.
[산업상의 이용 가능성]
본 발명은 서브 마운트 기판등의 전자 부품에 이용할 수 있다.
1A, 1B … 전자 부품, 10 … 기재,
20 … 적층체, 21, 22, 23 … 도전성 금속 재료층,
23a … 땜납층 배치 영역, 23b … 땜납층 비배치 영역,
23c … 슬릿, 30 … 땜납층,
40 … 배리어층.

Claims (6)

  1. 기재(基材)와,
    상기 기재상에 배치되어 있는, 복수의 도전성 금속 재료층의 적층체와,
    상기 적층체상에 배치되어 있는, Au－Sn 합금 땜납으로 이루어지는 땜납층을 구비하고,
    상기 적층체는 최외층(最外層)을 구성하는 상기 도전성 금속 재료층으로서, Au로 이루어지는 표면층을 가지고,
    상기 표면층은, 상기 땜납층이 배치되는 땜납층 배치 영역과, 상기 땜납층이 배치되지 않는 땜납층 비배치 영역을 포함하고,
    상기 땜납층 배치 영역과 상기 땜납층 비배치 영역은, 공간적으로 떨어져 있고,
    상기 땜납층 배치 영역과 상기 땜납층 비배치 영역이 공간적으로 떨어져 있는 영역에서는, 상기 표면층 아래의 상기 도전성 금속 재료층이 노출되어 있는 전자 부품.
  2. 청구항 1에 있어서,
    상기 땜납층 배치 영역은, 상기 땜납층 비배치 영역에 둘러싸이도록, 상기 땜납층 비배치 영역의 내측에 위치함과 아울러, 그 둘레 전체에 있어서 상기 땜납층 비배치 영역과 공간적으로 떨어져 있는 전자 부품.
  3. 청구항 1 또는 청구항 2에 있어서,
    상기 땜납층 배치 영역과 상기 땜납층 비배치 영역은, 상기 표면층에 형성된 슬릿에 의해 공간적으로 떨어져 있는 전자 부품.
  4. 청구항 1 또는 청구항 2에 있어서,
    상기 땜납층은 Pt로 이루어지는 배리어층을 매개로 하여, 상기 적층체상에 배치되어 있는 전자 부품.
  5. 청구항 1 또는 청구항 2에 있어서,
    상기 복수의 도전성 금속 재료층은 상기 기재와의 접촉층을 구성하고 있는 도전성 금속 재료층과, 해당 도전성 금속 재료층과 상기 표면층의 사이에 위치하고 있음과 아울러 배리어층을 구성하고 있는 도전성 금속 재료층을 포함하고,
    상기 땜납층 배치 영역과 상기 땜납층 비배치 영역이 공간적으로 떨어져 있는 상기 영역에서는, 상기 배리어층을 구성하고 있는 도전성 금속 재료층이 노출되어 있는 전자 부품.
  6. 청구항 1 또는 청구항 2에 있어서,
    상기 땜납층 배치 영역과 상기 땜납층 비배치 영역은, 상기 땜납층 비배치 영역의 Au가 상기 땜납층으로 확산되지 않도록 공간적으로 떨어져 있는 전자 부품.
KR1020167031733A 2014-08-07 2015-08-05 전자 부품 KR102387336B1 (ko)

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