KR102363138B1 - 기판 및 그 위에 배치된 층을 패턴화하는 방법 및 디바이스 구조체를 형성하는 방법 - Google Patents

기판 및 그 위에 배치된 층을 패턴화하는 방법 및 디바이스 구조체를 형성하는 방법 Download PDF

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KR102363138B1
KR102363138B1 KR1020197008831A KR20197008831A KR102363138B1 KR 102363138 B1 KR102363138 B1 KR 102363138B1 KR 1020197008831 A KR1020197008831 A KR 1020197008831A KR 20197008831 A KR20197008831 A KR 20197008831A KR 102363138 B1 KR102363138 B1 KR 102363138B1
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surface feature
substrate
ions
axis
layer
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KR20190045251A (ko
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스티븐 알. 셔먼
존 하우탈라
사이몬 러펠
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베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크.
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041Photolithographic processes
    • H01L21/0274
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441Optical proximity correction [OPC]
    • H01L21/3065
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Drying Of Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Micromachines (AREA)
KR1020197008831A 2016-09-22 2017-09-11 기판 및 그 위에 배치된 층을 패턴화하는 방법 및 디바이스 구조체를 형성하는 방법 Active KR102363138B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662398032P 2016-09-22 2016-09-22
US62/398,032 2016-09-22
US15/384,496 2016-12-20
US15/384,496 US10229832B2 (en) 2016-09-22 2016-12-20 Techniques for forming patterned features using directional ions
PCT/US2017/050958 WO2018057327A1 (en) 2016-09-22 2017-09-11 Techniques for forming patterned features using directional ions

Publications (2)

Publication Number Publication Date
KR20190045251A KR20190045251A (ko) 2019-05-02
KR102363138B1 true KR102363138B1 (ko) 2022-02-15

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Country Status (6)

Country Link
US (1) US10229832B2 (https=)
JP (1) JP6889773B2 (https=)
KR (1) KR102363138B1 (https=)
CN (1) CN109791874B (https=)
TW (1) TWI725230B (https=)
WO (1) WO2018057327A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10658184B2 (en) * 2016-12-15 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Pattern fidelity enhancement with directional patterning technology
US10861698B2 (en) 2017-08-29 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Pattern fidelity enhancement
US10546770B2 (en) 2018-05-02 2020-01-28 Varian Semiconductor Equipment Associates, Inc. Method and device isolation structure in finFET
US11004729B2 (en) 2018-06-27 2021-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices
US11796922B2 (en) 2019-09-30 2023-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices
US20260082879A1 (en) * 2024-09-18 2026-03-19 Tel Manufacturing And Engineering Of America, Inc. Directional sidewall deposition using directional beam

Family Cites Families (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process
US4484979A (en) 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
US4680085A (en) 1986-04-14 1987-07-14 Ovonic Imaging Systems, Inc. Method of forming thin film semiconductor devices
JPH04124809A (ja) * 1990-09-14 1992-04-24 Toppan Printing Co Ltd X線露光用マスクの製造方法
JP2932650B2 (ja) * 1990-09-17 1999-08-09 松下電器産業株式会社 微細構造物の製造方法
JP2757838B2 (ja) 1995-10-25 1998-05-25 日本電気株式会社 半導体装置の製造方法
JP3053072B2 (ja) * 1996-09-10 2000-06-19 東京応化工業株式会社 レジスト積層体及びそれを用いたパターン形成方法
US6414366B1 (en) 1998-07-29 2002-07-02 Tdk Corporation Thin-film magnetic head wafer and manufacturing method of thin-film magnetic head
JP2000122267A (ja) * 1998-10-14 2000-04-28 Nikon Corp ステンシル型レチクルのリペア方法
US6238582B1 (en) 1999-03-30 2001-05-29 Veeco Instruments, Inc. Reactive ion beam etching method and a thin film head fabricated using the method
US6787052B1 (en) 2000-06-19 2004-09-07 Vladimir Vaganov Method for fabricating microstructures with deep anisotropic etching of thick silicon wafers
US6998219B2 (en) * 2001-06-27 2006-02-14 University Of South Florida Maskless photolithography for etching and deposition
DE10205077B4 (de) 2002-02-07 2007-03-08 Infineon Technologies Ag Halbleiterspeicherzelle mit einem Graben und einem planaren Auswahltransistor und Verfahren zu ihrer Herstellung
US7041598B2 (en) * 2003-06-25 2006-05-09 Hewlett-Packard Development Company, L.P. Directional ion etching process for patterning self-aligned via contacts
US6794256B1 (en) 2003-08-04 2004-09-21 Advanced Micro Devices Inc. Method for asymmetric spacer formation
JP4054325B2 (ja) 2004-08-11 2008-02-27 日本電信電話株式会社 半導体素子の作製方法及び半導体素子
US20080002749A1 (en) 2004-09-29 2008-01-03 California Institute Of Technology Material processing method for semiconductor lasers
KR100708530B1 (ko) 2004-12-31 2007-04-16 동부일렉트로닉스 주식회사 얕은 트랜치 소자 분리막 공정 중 디봇 형상 방지방법
JP4867171B2 (ja) 2005-01-21 2012-02-01 富士電機株式会社 半導体装置の製造方法
US7696102B2 (en) 2005-03-31 2010-04-13 Gang Zhang Methods for fabrication of three-dimensional structures
US20070051622A1 (en) 2005-09-02 2007-03-08 Applied Materials, Inc. Simultaneous ion milling and sputter deposition
US7323374B2 (en) * 2005-09-19 2008-01-29 International Business Machines Corporation Dense chevron finFET and method of manufacturing same
US7790621B2 (en) 2006-02-23 2010-09-07 Sophia Wen Ion implantation for increasing etch rate differential between adjacent materials
KR20070122050A (ko) * 2006-06-23 2007-12-28 주식회사 하이닉스반도체 이중 패터닝 공정을 이용한 캐패시터 패턴 형성 방법
US7542497B2 (en) 2006-07-18 2009-06-02 Binoptics Corporation AlGaInN-based lasers with dovetailed ridge
US7892928B2 (en) 2007-03-23 2011-02-22 International Business Machines Corporation Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers
US8652763B2 (en) 2007-07-16 2014-02-18 The Board Of Trustees Of The University Of Illinois Method for fabricating dual damascene profiles using sub pixel-voting lithography and devices made by same
US7625790B2 (en) * 2007-07-26 2009-12-01 International Business Machines Corporation FinFET with sublithographic fin width
US20090084757A1 (en) 2007-09-28 2009-04-02 Yuri Erokhin Uniformity control for ion beam assisted etching
US7994002B2 (en) 2008-11-24 2011-08-09 Applied Materials, Inc. Method and apparatus for trench and via profile modification
US7862962B2 (en) * 2009-01-20 2011-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit layout design
US7767977B1 (en) 2009-04-03 2010-08-03 Varian Semiconductor Equipment Associates, Inc. Ion source
US8603591B2 (en) 2009-04-03 2013-12-10 Varian Semiconductor Ewuipment Associates, Inc. Enhanced etch and deposition profile control using plasma sheath engineering
US8101510B2 (en) 2009-04-03 2012-01-24 Varian Semiconductor Equipment Associates, Inc. Plasma processing apparatus
US8192641B2 (en) 2009-07-23 2012-06-05 GlobalFoundries, Inc. Methods for fabricating non-planar electronic devices having sidewall spacers formed adjacent selected surfaces
JP5011360B2 (ja) * 2009-09-21 2012-08-29 株式会社東芝 フォトマスクの設計方法
US8089050B2 (en) 2009-11-19 2012-01-03 Twin Creeks Technologies, Inc. Method and apparatus for modifying a ribbon-shaped ion beam
US8778603B2 (en) * 2010-03-15 2014-07-15 Varian Semiconductor Equipment Associates, Inc. Method and system for modifying substrate relief features using ion implantation
US8421139B2 (en) 2010-04-07 2013-04-16 International Business Machines Corporation Structure and method to integrate embedded DRAM with finfet
US8252691B2 (en) * 2010-04-14 2012-08-28 Asm Genitech Korea Ltd. Method of forming semiconductor patterns
US8288741B1 (en) 2011-08-16 2012-10-16 Varian Semiconductor Equipment Associates, Inc. Apparatus and method for three dimensional ion processing
US8339752B1 (en) 2011-09-26 2012-12-25 Hitachi Global Storage Technologies Netherlands B.V. Magnetic head with wide sensor back edge, low resistance, and high signal to-noise ratio and methods of production thereof
US8881066B2 (en) * 2011-12-29 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Mandrel modification for achieving single fin fin-like field effect transistor (FinFET) device
US9252021B2 (en) * 2012-02-09 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for patterning a plurality of features for Fin-like field-effect transistor (FinFET) devices
US8765608B2 (en) * 2012-05-01 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming trenches
US9653309B2 (en) 2012-05-25 2017-05-16 The Regents Of The University Of California Method for fabrication of high aspect ratio trenches and formation of nanoscale features therefrom
US8637365B2 (en) 2012-06-06 2014-01-28 International Business Machines Corporation Spacer isolation in deep trench
CN104584196B (zh) * 2012-06-29 2017-02-22 佳能安内华股份有限公司 离子束处理方法和离子束处理装置
US9118001B2 (en) 2012-07-11 2015-08-25 Varian Semiconductor Equipment Associates, Inc. Techniques for treating sidewalls of patterned structures using angled ion treatment
US9190498B2 (en) 2012-09-14 2015-11-17 Varian Semiconductor Equipment Associates, Inc. Technique for forming a FinFET device using selective ion implantation
US9287178B2 (en) 2012-10-01 2016-03-15 Globalfoundries Inc. Multi-gate field effect transistor (FET) including isolated fin body
US9337271B2 (en) 2012-12-28 2016-05-10 Mitsubishi Electric Corporation Silicon-carbide semiconductor device and manufacturing method therefor
CN105008891B (zh) 2013-01-11 2018-02-06 Fei公司 用于变更蚀刻速率的离子注入
US9153478B2 (en) 2013-03-15 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer etching process for integrated circuit design
US8791024B1 (en) * 2013-05-14 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method to define multiple layer patterns using a single exposure
US20140357080A1 (en) 2013-06-04 2014-12-04 Tokyo Electron Limited Method for preferential shrink and bias control in contact shrink etch
KR101509529B1 (ko) 2013-07-31 2015-04-07 아주대학교산학협력단 3차원 형태의 구리 나노구조물 및 그 형성 방법
US9934981B2 (en) 2013-09-26 2018-04-03 Varian Semiconductor Equipment Associates, Inc. Techniques for processing substrates using directional reactive ion etching
US9287123B2 (en) 2014-04-28 2016-03-15 Varian Semiconductor Equipment Associates, Inc. Techniques for forming angled structures for reduced defects in heteroepitaxy of semiconductor films
US10008384B2 (en) * 2015-06-25 2018-06-26 Varian Semiconductor Equipment Associates, Inc. Techniques to engineer nanoscale patterned features using ions

Also Published As

Publication number Publication date
JP2019530222A (ja) 2019-10-17
WO2018057327A1 (en) 2018-03-29
US10229832B2 (en) 2019-03-12
CN109791874B (zh) 2022-11-29
TW201822247A (zh) 2018-06-16
US20180082844A1 (en) 2018-03-22
JP6889773B2 (ja) 2021-06-18
CN109791874A (zh) 2019-05-21
KR20190045251A (ko) 2019-05-02
TWI725230B (zh) 2021-04-21

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