KR101956615B1 - 고속 워드 라인 디코더 및 레벨-시프터 - Google Patents
고속 워드 라인 디코더 및 레벨-시프터 Download PDFInfo
- Publication number
- KR101956615B1 KR101956615B1 KR1020177025630A KR20177025630A KR101956615B1 KR 101956615 B1 KR101956615 B1 KR 101956615B1 KR 1020177025630 A KR1020177025630 A KR 1020177025630A KR 20177025630 A KR20177025630 A KR 20177025630A KR 101956615 B1 KR101956615 B1 KR 101956615B1
- Authority
- KR
- South Korea
- Prior art keywords
- power supply
- gate
- supply voltage
- word line
- decoded signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562133840P | 2015-03-16 | 2015-03-16 | |
| US62/133,840 | 2015-03-16 | ||
| US15/070,963 | 2016-03-15 | ||
| US15/070,963 US9940987B2 (en) | 2015-03-16 | 2016-03-15 | High-speed word line decoder and level-shifter |
| PCT/US2016/022593 WO2016149333A1 (en) | 2015-03-16 | 2016-03-16 | High-speed word line decoder and level-shifter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20170128299A KR20170128299A (ko) | 2017-11-22 |
| KR101956615B1 true KR101956615B1 (ko) | 2019-03-11 |
Family
ID=55661580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020177025630A Expired - Fee Related KR101956615B1 (ko) | 2015-03-16 | 2016-03-16 | 고속 워드 라인 디코더 및 레벨-시프터 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9940987B2 (https=) |
| EP (1) | EP3271919B1 (https=) |
| JP (1) | JP6352552B2 (https=) |
| KR (1) | KR101956615B1 (https=) |
| CN (1) | CN107430876B (https=) |
| WO (1) | WO2016149333A1 (https=) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104811634B (zh) * | 2013-12-29 | 2018-07-31 | 芯视达系统公司 | 支持多种电压的紧凑型行解码器 |
| US10037290B1 (en) * | 2016-06-02 | 2018-07-31 | Marvell International Ltd. | Dual-port memories and input/output circuits for preventing failures corresponding to concurrent accesses of dual-port memory cells |
| US10109365B2 (en) * | 2016-11-28 | 2018-10-23 | Taiwan Semiconductor Manufacturing Company Limited | Word line driver |
| US11114148B1 (en) * | 2020-04-16 | 2021-09-07 | Wuxi Petabyte Technologies Co., Ltd. | Efficient ferroelectric random-access memory wordline driver, decoder, and related circuits |
| US11264093B1 (en) | 2020-08-25 | 2022-03-01 | Taiwan Semiconductor Manufacturing Company Limited | Duo-level word line driver |
| US12165693B2 (en) * | 2021-12-03 | 2024-12-10 | Micron Technology, Inc. | Circuitry including a level shifter and logic, configured to receive a power up reset signal, and associated methods, devices, and systems |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6031781A (en) | 1998-12-21 | 2000-02-29 | Mitisubishi Denki Kabushiki Kaisha | Semiconductor memory device allowing high-speed activation of internal circuit |
| WO2013147742A1 (en) | 2012-03-26 | 2013-10-03 | Intel Corporation | Methods and systems to selectively boost an operating voltage of, and controls to an 8t bit-cell array and/or other logic blocks |
| US20140159773A1 (en) | 2012-12-07 | 2014-06-12 | Ken Keon Shin | Integrated circuit including circuits driven in different voltage domains |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004334982A (ja) * | 2003-05-08 | 2004-11-25 | Nec Electronics Corp | 行デコーダ、半導体回路装置 |
| JP4496069B2 (ja) * | 2004-12-20 | 2010-07-07 | 株式会社東芝 | Mos型半導体集積回路装置 |
| US7176725B2 (en) * | 2005-02-04 | 2007-02-13 | International Business Machines Corporation | Fast pulse powered NOR decode apparatus for semiconductor devices |
| US7463545B2 (en) | 2006-03-17 | 2008-12-09 | Texas Instruments Incorporated | System and method for reducing latency in a memory array decoder circuit |
| JP2008084457A (ja) | 2006-09-28 | 2008-04-10 | Toshiba Corp | 不揮発性半導体記憶装置 |
| JP2008152845A (ja) * | 2006-12-15 | 2008-07-03 | Toshiba Corp | 半導体記憶装置 |
| JP4913878B2 (ja) * | 2009-05-27 | 2012-04-11 | ルネサスエレクトロニクス株式会社 | ワード線選択回路、ロウデコーダ |
| US8391097B2 (en) | 2010-05-25 | 2013-03-05 | Taiwan Semiconductor Manufacturing Co. Ltd. | Memory word-line driver having reduced power consumption |
| KR101753251B1 (ko) | 2010-07-23 | 2017-07-05 | 삼성전자주식회사 | 음전압 레벨 쉬프터를 포함하는 스태틱 랜덤 액세스 메모리 장치 |
| US8456946B2 (en) | 2010-12-22 | 2013-06-04 | Intel Corporation | NAND logic word line selection |
| US8971133B1 (en) | 2013-09-26 | 2015-03-03 | Arm Limited | Memory device and method of operation of such a memory device |
-
2016
- 2016-03-15 US US15/070,963 patent/US9940987B2/en active Active
- 2016-03-16 JP JP2017548466A patent/JP6352552B2/ja not_active Expired - Fee Related
- 2016-03-16 WO PCT/US2016/022593 patent/WO2016149333A1/en not_active Ceased
- 2016-03-16 EP EP16714646.3A patent/EP3271919B1/en active Active
- 2016-03-16 KR KR1020177025630A patent/KR101956615B1/ko not_active Expired - Fee Related
- 2016-03-16 CN CN201680015459.6A patent/CN107430876B/zh active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6031781A (en) | 1998-12-21 | 2000-02-29 | Mitisubishi Denki Kabushiki Kaisha | Semiconductor memory device allowing high-speed activation of internal circuit |
| WO2013147742A1 (en) | 2012-03-26 | 2013-10-03 | Intel Corporation | Methods and systems to selectively boost an operating voltage of, and controls to an 8t bit-cell array and/or other logic blocks |
| US20140159773A1 (en) | 2012-12-07 | 2014-06-12 | Ken Keon Shin | Integrated circuit including circuits driven in different voltage domains |
Also Published As
| Publication number | Publication date |
|---|---|
| EP3271919A1 (en) | 2018-01-24 |
| JP6352552B2 (ja) | 2018-07-04 |
| CN107430876A (zh) | 2017-12-01 |
| CN107430876B (zh) | 2020-12-11 |
| KR20170128299A (ko) | 2017-11-22 |
| US9940987B2 (en) | 2018-04-10 |
| US20160276005A1 (en) | 2016-09-22 |
| JP2018513520A (ja) | 2018-05-24 |
| WO2016149333A1 (en) | 2016-09-22 |
| EP3271919B1 (en) | 2019-05-01 |
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