KR101825114B1 - 출력 버퍼와 상기 출력 버퍼를 포함하는 장치들 - Google Patents

출력 버퍼와 상기 출력 버퍼를 포함하는 장치들 Download PDF

Info

Publication number
KR101825114B1
KR101825114B1 KR1020110115101A KR20110115101A KR101825114B1 KR 101825114 B1 KR101825114 B1 KR 101825114B1 KR 1020110115101 A KR1020110115101 A KR 1020110115101A KR 20110115101 A KR20110115101 A KR 20110115101A KR 101825114 B1 KR101825114 B1 KR 101825114B1
Authority
KR
South Korea
Prior art keywords
voltage
circuit
control signal
sourcing
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020110115101A
Other languages
English (en)
Korean (ko)
Other versions
KR20130049998A (ko
Inventor
이승호
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020110115101A priority Critical patent/KR101825114B1/ko
Priority to US13/536,471 priority patent/US8791722B2/en
Priority to CN201210427356.4A priority patent/CN103095281B/zh
Priority to JP2012241973A priority patent/JP5963644B2/ja
Publication of KR20130049998A publication Critical patent/KR20130049998A/ko
Application granted granted Critical
Publication of KR101825114B1 publication Critical patent/KR101825114B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
KR1020110115101A 2011-11-07 2011-11-07 출력 버퍼와 상기 출력 버퍼를 포함하는 장치들 Expired - Fee Related KR101825114B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020110115101A KR101825114B1 (ko) 2011-11-07 2011-11-07 출력 버퍼와 상기 출력 버퍼를 포함하는 장치들
US13/536,471 US8791722B2 (en) 2011-11-07 2012-06-28 Output buffer, operating method thereof and devices including the same
CN201210427356.4A CN103095281B (zh) 2011-11-07 2012-10-31 输出缓冲器，其操作方法及包括输出缓冲器的设备
JP2012241973A JP5963644B2 (ja) 2011-11-07 2012-11-01 出力バッファ回路の動作方法、その動作方法を用いる出力バッファ回路、その出力バッファ回路を含むシステムオンチップ、及びその出力バッファ回路を含む携帯用データ処理装置。

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110115101A KR101825114B1 (ko) 2011-11-07 2011-11-07 출력 버퍼와 상기 출력 버퍼를 포함하는 장치들

Publications (2)

Publication Number Publication Date
KR20130049998A KR20130049998A (ko) 2013-05-15
KR101825114B1 true KR101825114B1 (ko) 2018-03-14

Family

ID=48207490

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110115101A Expired - Fee Related KR101825114B1 (ko) 2011-11-07 2011-11-07 출력 버퍼와 상기 출력 버퍼를 포함하는 장치들

Country Status (4)

Country Link
US (1) US8791722B2 (https=)
JP (1) JP5963644B2 (https=)
KR (1) KR101825114B1 (https=)
CN (1) CN103095281B (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112013007285B4 (de) * 2013-09-24 2024-06-13 Intel Corporation Gegen eine hohe Spannung tolerante Eingangsspannungs-Pufferschaltung
US9362912B2 (en) * 2014-03-25 2016-06-07 SK Hynix Inc. Data output circuit of semiconductor apparatus
US9746866B2 (en) * 2014-05-22 2017-08-29 Mediatek Inc. Control circuit and control system
US9419615B2 (en) * 2015-01-20 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Driver circuit
CN106788386B (zh) * 2016-11-30 2021-08-06 上海华力微电子有限公司 一种降低热载流子劣化的电平转换电路
US10128835B2 (en) * 2017-02-20 2018-11-13 Stmicroelectronics International N.V. Aging tolerant I/O driver
US10484041B2 (en) * 2017-09-13 2019-11-19 Xilinx, Inc. Glitch-free wide supply range transceiver for integrated circuits
US10903840B2 (en) * 2018-04-02 2021-01-26 Mediatek Inc. Pad tracking circuit for high-voltage input-tolerant output buffer
CN111524542B (zh) * 2019-02-01 2022-04-01 华邦电子股份有限公司 缓冲输出电路及其驱动方法
US10911044B1 (en) * 2019-12-05 2021-02-02 Integrated Silicon Solution, (Cayman) Inc. Wide range output driver circuit for semiconductor device
KR102702558B1 (ko) * 2022-01-24 2024-09-04 주식회사 피델릭스 출력 신호의 스윙폭 조절이 용이한 출력 버퍼 회로
KR102694728B1 (ko) * 2022-07-18 2024-08-13 주식회사 피델릭스 전송 데이터 신호의 스윙폭을 감소하여 전류 소모를 저감하는 반도체 메모리 장치의 데이터 전송 시스템

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5124585A (en) * 1991-01-16 1992-06-23 Jun Kim Pulsed bootstrapping output buffer and associated method
US5332932A (en) * 1991-09-16 1994-07-26 Advanced Micro Devices, Inc. Output driver circuit having reduced VSS/VDD voltage fluctuations
US5220209A (en) * 1991-09-27 1993-06-15 National Semiconductor Corporation Edge rate controlled output buffer circuit with controlled charge storage
KR960006911B1 (ko) * 1992-12-31 1996-05-25 현대전자산업주식회사 데이타 출력버퍼
US5331593A (en) * 1993-03-03 1994-07-19 Micron Semiconductor, Inc. Read circuit for accessing dynamic random access memories (DRAMS)
KR960009247B1 (en) * 1993-06-08 1996-07-16 Samsung Electronics Co Ltd Data output buffer of semiconductor integrated circuit
JP3138680B2 (ja) 1998-03-13 2001-02-26 日本電気アイシーマイコンシステム株式会社 出力バッファ制御回路
US6288563B1 (en) * 1998-12-31 2001-09-11 Intel Corporation Slew rate control
KR100310418B1 (ko) * 1999-01-18 2001-11-02 김영환 데이타 출력버퍼
JP3670563B2 (ja) * 2000-09-18 2005-07-13 株式会社東芝 半導体装置
US6624716B2 (en) * 2002-01-03 2003-09-23 Raytheon Company Microstrip to circular waveguide transition with a stripline portion
KR100810611B1 (ko) 2006-05-15 2008-03-07 삼성전자주식회사 반도체 장치의 레벨 쉬프팅 회로
JP5262217B2 (ja) 2008-03-24 2013-08-14 セイコーエプソン株式会社 電圧選択回路、電気泳動表示装置、及び電子機器
US8344760B2 (en) * 2008-07-17 2013-01-01 Ati Technologies Ulc Input/output buffer circuit
KR101109131B1 (ko) 2008-11-14 2012-02-15 한국과학기술원 전압 제어 장치 및 구동 방법
US7759977B1 (en) * 2009-06-08 2010-07-20 Mediatek Inc. Buffering circuit

Also Published As

Publication number Publication date
CN103095281A (zh) 2013-05-08
US8791722B2 (en) 2014-07-29
KR20130049998A (ko) 2013-05-15
JP2013102430A (ja) 2013-05-23
CN103095281B (zh) 2018-01-23
JP5963644B2 (ja) 2016-08-03
US20130113542A1 (en) 2013-05-09

Similar Documents

Publication Publication Date Title
KR101825114B1 (ko) 출력 버퍼와 상기 출력 버퍼를 포함하는 장치들
CN108932960B (zh) 控制片内终结器的方法和执行该方法的系统
CN102157188B (zh) 集成电路和用于集成电路的方法
US8164971B2 (en) Dual power rail word line driver and dual power rail word line driver array
US9245651B2 (en) Memory device for masking read data and a method of testing the same
KR101293528B1 (ko) 듀얼-기술 트랜지스터들을 사용한 저누설 고성능 정적 랜덤 액세스 메모리 셀
JP5380332B2 (ja) 半導体装置及びデータプロセッサ
US9281048B2 (en) Semiconductor memory device capable of preventing negative bias temperature instability (NBTI) using self refresh information
JP2012239041A (ja) 半導体装置
KR20200020048A (ko) 반도체 메모리 장치, 이의 동작 방법 및 이를 포함하는 시스템
US9076510B2 (en) Power mixing circuit and semiconductor memory device including the same
CN107154271B (zh) 静态存储器装置及其静态存储器胞
KR101020293B1 (ko) 반도체 메모리 장치
JP2009076169A (ja) 半導体記憶装置
US7554857B2 (en) Data output multiplexer
CN101847991B (zh) 时钟脉冲产生器、存储器电路及产生内部时钟脉冲信号的方法
KR20150080898A (ko) 반도체장치
US6998873B2 (en) Data input/output buffer and semiconductor memory device using the same
US7495981B2 (en) Internal voltage generator
KR20090007122A (ko) 보안기능을 갖는 레지스터 및 이를 구비하는 컴퓨터 시스템
US7006389B2 (en) Voltage translator for multiple voltage operations
CN119229917A (zh) 泄漏补偿的动态锁存器
KR20070076112A (ko) 레벨 쉬프터
KR20190093099A (ko) 출력 드라이브 회로의 열화를 방지하는 전송부를 포함하는 반도체 장치
KR20060008616A (ko) 입출력 선택신호 발생기

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20210130

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20210130