KR101662218B1 - 다중 깊이 sti 방법 - Google Patents

다중 깊이 sti 방법 Download PDF

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Publication number
KR101662218B1
KR101662218B1 KR1020117007448A KR20117007448A KR101662218B1 KR 101662218 B1 KR101662218 B1 KR 101662218B1 KR 1020117007448 A KR1020117007448 A KR 1020117007448A KR 20117007448 A KR20117007448 A KR 20117007448A KR 101662218 B1 KR101662218 B1 KR 101662218B1
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KR
South Korea
Prior art keywords
trenches
etching
masking layer
thickness
region
Prior art date
Application number
KR1020117007448A
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English (en)
Korean (ko)
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KR20110102872A (ko
Inventor
저스틴 에이치. 사토
브라이언 헤네스
그레그 스톰
로버트 피. 마
월터 이. 런디
Original Assignee
마이크로칩 테크놀로지 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 마이크로칩 테크놀로지 인코포레이티드 filed Critical 마이크로칩 테크놀로지 인코포레이티드
Publication of KR20110102872A publication Critical patent/KR20110102872A/ko
Application granted granted Critical
Publication of KR101662218B1 publication Critical patent/KR101662218B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
KR1020117007448A 2009-01-16 2010-01-13 다중 깊이 sti 방법 KR101662218B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US14535409P 2009-01-16 2009-01-16
US61/145,354 2009-01-16
US12/685,998 2010-01-12
US12/685,998 US8853091B2 (en) 2009-01-16 2010-01-12 Method for manufacturing a semiconductor die with multiple depth shallow trench isolation
PCT/US2010/020845 WO2010083184A1 (fr) 2009-01-16 2010-01-13 Procédé d'isolation par tranchées de diverses profondeurs, mais toujours peu profondes

Publications (2)

Publication Number Publication Date
KR20110102872A KR20110102872A (ko) 2011-09-19
KR101662218B1 true KR101662218B1 (ko) 2016-10-04

Family

ID=42337311

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020117007448A KR101662218B1 (ko) 2009-01-16 2010-01-13 다중 깊이 sti 방법

Country Status (7)

Country Link
US (1) US8853091B2 (fr)
EP (1) EP2387797B1 (fr)
KR (1) KR101662218B1 (fr)
CN (1) CN102282666B (fr)
IL (1) IL211840A0 (fr)
TW (1) TWI476861B (fr)
WO (1) WO2010083184A1 (fr)

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US9093296B2 (en) 2012-02-09 2015-07-28 United Microelectronics Corp. LDMOS transistor having trench structures extending to a buried layer
US8575035B2 (en) * 2012-02-22 2013-11-05 Omnivision Technologies, Inc. Methods of forming varying depth trenches in semiconductor devices
US8633099B1 (en) * 2012-07-19 2014-01-21 Macronix International Co., Ltd. Method for forming interlayer connectors in a three-dimensional stacked IC device
US8703577B1 (en) * 2012-12-17 2014-04-22 United Microelectronics Corp. Method for fabrication deep trench isolation structure
US9214351B2 (en) 2013-03-12 2015-12-15 Macronix International Co., Ltd. Memory architecture of thin film 3D array
US20140327084A1 (en) 2013-05-01 2014-11-06 International Business Machines Corporation Dual shallow trench isolation (sti) field effect transistor (fet) and methods of forming
US9324603B2 (en) * 2013-08-15 2016-04-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structures with shallow trench isolations
CN103558903A (zh) * 2013-11-12 2014-02-05 上海航天测控通信研究所 一种具有抗辐性能的PowerPC计算机模块
US9318368B2 (en) * 2013-11-14 2016-04-19 Taiwan Semiconductor Manufacturing Co., Ltd. Photomask and method for forming dual STI structure by using the same
US9761486B2 (en) * 2014-03-31 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of chip packaging
KR20160029900A (ko) * 2014-09-05 2016-03-16 삼성전자주식회사 반도체 소자의 제조 방법
KR102398862B1 (ko) 2015-05-13 2022-05-16 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN105161450B (zh) * 2015-07-30 2018-08-28 上海华力微电子有限公司 一种双浅沟槽隔离形成方法
US9799605B2 (en) 2015-11-25 2017-10-24 International Business Machines Corporation Advanced copper interconnects with hybrid microstructure
US9680010B1 (en) 2016-02-04 2017-06-13 United Microelectronics Corp. High voltage device and method of fabricating the same
US20170287834A1 (en) * 2016-03-29 2017-10-05 Microchip Technology Incorporated Contact Expose Etch Stop
US10304721B1 (en) * 2017-12-30 2019-05-28 Texas Instruments Incorporated Formation of isolation layers using a dry-wet-dry oxidation technique
CN110364525B (zh) * 2018-04-10 2021-10-08 世界先进积体电路股份有限公司 半导体结构及其制造方法
US10796969B2 (en) * 2018-09-07 2020-10-06 Kla-Tencor Corporation System and method for fabricating semiconductor wafer features having controlled dimensions
US11158533B2 (en) 2018-11-07 2021-10-26 Vanguard International Semiconductor Corporation Semiconductor structures and fabrication method thereof
CN111627809B (zh) * 2019-02-28 2024-03-22 东京毅力科创株式会社 基片处理方法和基片处理装置
FR3102296A1 (fr) * 2019-10-16 2021-04-23 Stmicroelectronics (Rousset) Sas Procédé de fabrication de circuit intégré comprenant une phase de formation de tranchées dans un substrat et circuit intégré correspondant.
CN114724944A (zh) * 2022-05-19 2022-07-08 晶芯成(北京)科技有限公司 一种半导体结构的制造方法

Citations (3)

* Cited by examiner, † Cited by third party
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US20020022327A1 (en) 2000-08-16 2002-02-21 Hyundai Electronics Industries Co., Ltd. Method for fabricating a semiconductor device having an elevated source/drain scheme
US20040029385A1 (en) 2002-04-30 2004-02-12 Dirk Manger Semiconductor substrate with trenches of varying depth
US20040092115A1 (en) 2002-11-07 2004-05-13 Winbond Electronics Corp. Memory device having isolation trenches with different depths and the method for making the same

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US5705321A (en) * 1993-09-30 1998-01-06 The University Of New Mexico Method for manufacture of quantum sized periodic structures in Si materials
KR100290852B1 (ko) * 1999-04-29 2001-05-15 구자홍 에칭 방법
US6277752B1 (en) 1999-06-28 2001-08-21 Taiwan Semiconductor Manufacturing Company Multiple etch method for forming residue free patterned hard mask layer
US6864152B1 (en) * 2003-05-20 2005-03-08 Lsi Logic Corporation Fabrication of trenches with multiple depths on the same substrate
KR100649315B1 (ko) * 2005-09-20 2006-11-24 동부일렉트로닉스 주식회사 플래시 메모리의 소자분리막 제조 방법
US7750429B2 (en) 2007-05-15 2010-07-06 International Business Machines Corporation Self-aligned and extended inter-well isolation structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020022327A1 (en) 2000-08-16 2002-02-21 Hyundai Electronics Industries Co., Ltd. Method for fabricating a semiconductor device having an elevated source/drain scheme
US20040029385A1 (en) 2002-04-30 2004-02-12 Dirk Manger Semiconductor substrate with trenches of varying depth
US20040092115A1 (en) 2002-11-07 2004-05-13 Winbond Electronics Corp. Memory device having isolation trenches with different depths and the method for making the same

Also Published As

Publication number Publication date
US8853091B2 (en) 2014-10-07
IL211840A0 (en) 2011-06-30
EP2387797A1 (fr) 2011-11-23
US20100184295A1 (en) 2010-07-22
CN102282666B (zh) 2014-12-17
CN102282666A (zh) 2011-12-14
TW201036107A (en) 2010-10-01
WO2010083184A1 (fr) 2010-07-22
KR20110102872A (ko) 2011-09-19
TWI476861B (zh) 2015-03-11
EP2387797B1 (fr) 2019-03-06

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