KR101662218B1 - 다중 깊이 sti 방법 - Google Patents
다중 깊이 sti 방법 Download PDFInfo
- Publication number
- KR101662218B1 KR101662218B1 KR1020117007448A KR20117007448A KR101662218B1 KR 101662218 B1 KR101662218 B1 KR 101662218B1 KR 1020117007448 A KR1020117007448 A KR 1020117007448A KR 20117007448 A KR20117007448 A KR 20117007448A KR 101662218 B1 KR101662218 B1 KR 101662218B1
- Authority
- KR
- South Korea
- Prior art keywords
- trenches
- etching
- masking layer
- thickness
- region
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14535409P | 2009-01-16 | 2009-01-16 | |
US61/145,354 | 2009-01-16 | ||
US12/685,998 | 2010-01-12 | ||
US12/685,998 US8853091B2 (en) | 2009-01-16 | 2010-01-12 | Method for manufacturing a semiconductor die with multiple depth shallow trench isolation |
PCT/US2010/020845 WO2010083184A1 (fr) | 2009-01-16 | 2010-01-13 | Procédé d'isolation par tranchées de diverses profondeurs, mais toujours peu profondes |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20110102872A KR20110102872A (ko) | 2011-09-19 |
KR101662218B1 true KR101662218B1 (ko) | 2016-10-04 |
Family
ID=42337311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020117007448A KR101662218B1 (ko) | 2009-01-16 | 2010-01-13 | 다중 깊이 sti 방법 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8853091B2 (fr) |
EP (1) | EP2387797B1 (fr) |
KR (1) | KR101662218B1 (fr) |
CN (1) | CN102282666B (fr) |
IL (1) | IL211840A0 (fr) |
TW (1) | TWI476861B (fr) |
WO (1) | WO2010083184A1 (fr) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9093296B2 (en) | 2012-02-09 | 2015-07-28 | United Microelectronics Corp. | LDMOS transistor having trench structures extending to a buried layer |
US8575035B2 (en) * | 2012-02-22 | 2013-11-05 | Omnivision Technologies, Inc. | Methods of forming varying depth trenches in semiconductor devices |
US8633099B1 (en) * | 2012-07-19 | 2014-01-21 | Macronix International Co., Ltd. | Method for forming interlayer connectors in a three-dimensional stacked IC device |
US8703577B1 (en) * | 2012-12-17 | 2014-04-22 | United Microelectronics Corp. | Method for fabrication deep trench isolation structure |
US9214351B2 (en) | 2013-03-12 | 2015-12-15 | Macronix International Co., Ltd. | Memory architecture of thin film 3D array |
US20140327084A1 (en) | 2013-05-01 | 2014-11-06 | International Business Machines Corporation | Dual shallow trench isolation (sti) field effect transistor (fet) and methods of forming |
US9324603B2 (en) * | 2013-08-15 | 2016-04-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structures with shallow trench isolations |
CN103558903A (zh) * | 2013-11-12 | 2014-02-05 | 上海航天测控通信研究所 | 一种具有抗辐性能的PowerPC计算机模块 |
US9318368B2 (en) * | 2013-11-14 | 2016-04-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Photomask and method for forming dual STI structure by using the same |
US9761486B2 (en) * | 2014-03-31 | 2017-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of chip packaging |
KR20160029900A (ko) * | 2014-09-05 | 2016-03-16 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
KR102398862B1 (ko) | 2015-05-13 | 2022-05-16 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN105161450B (zh) * | 2015-07-30 | 2018-08-28 | 上海华力微电子有限公司 | 一种双浅沟槽隔离形成方法 |
US9799605B2 (en) | 2015-11-25 | 2017-10-24 | International Business Machines Corporation | Advanced copper interconnects with hybrid microstructure |
US9680010B1 (en) | 2016-02-04 | 2017-06-13 | United Microelectronics Corp. | High voltage device and method of fabricating the same |
US20170287834A1 (en) * | 2016-03-29 | 2017-10-05 | Microchip Technology Incorporated | Contact Expose Etch Stop |
US10304721B1 (en) * | 2017-12-30 | 2019-05-28 | Texas Instruments Incorporated | Formation of isolation layers using a dry-wet-dry oxidation technique |
CN110364525B (zh) * | 2018-04-10 | 2021-10-08 | 世界先进积体电路股份有限公司 | 半导体结构及其制造方法 |
US10796969B2 (en) * | 2018-09-07 | 2020-10-06 | Kla-Tencor Corporation | System and method for fabricating semiconductor wafer features having controlled dimensions |
US11158533B2 (en) | 2018-11-07 | 2021-10-26 | Vanguard International Semiconductor Corporation | Semiconductor structures and fabrication method thereof |
CN111627809B (zh) * | 2019-02-28 | 2024-03-22 | 东京毅力科创株式会社 | 基片处理方法和基片处理装置 |
FR3102296A1 (fr) * | 2019-10-16 | 2021-04-23 | Stmicroelectronics (Rousset) Sas | Procédé de fabrication de circuit intégré comprenant une phase de formation de tranchées dans un substrat et circuit intégré correspondant. |
CN114724944A (zh) * | 2022-05-19 | 2022-07-08 | 晶芯成(北京)科技有限公司 | 一种半导体结构的制造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020022327A1 (en) | 2000-08-16 | 2002-02-21 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a semiconductor device having an elevated source/drain scheme |
US20040029385A1 (en) | 2002-04-30 | 2004-02-12 | Dirk Manger | Semiconductor substrate with trenches of varying depth |
US20040092115A1 (en) | 2002-11-07 | 2004-05-13 | Winbond Electronics Corp. | Memory device having isolation trenches with different depths and the method for making the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5705321A (en) * | 1993-09-30 | 1998-01-06 | The University Of New Mexico | Method for manufacture of quantum sized periodic structures in Si materials |
KR100290852B1 (ko) * | 1999-04-29 | 2001-05-15 | 구자홍 | 에칭 방법 |
US6277752B1 (en) | 1999-06-28 | 2001-08-21 | Taiwan Semiconductor Manufacturing Company | Multiple etch method for forming residue free patterned hard mask layer |
US6864152B1 (en) * | 2003-05-20 | 2005-03-08 | Lsi Logic Corporation | Fabrication of trenches with multiple depths on the same substrate |
KR100649315B1 (ko) * | 2005-09-20 | 2006-11-24 | 동부일렉트로닉스 주식회사 | 플래시 메모리의 소자분리막 제조 방법 |
US7750429B2 (en) | 2007-05-15 | 2010-07-06 | International Business Machines Corporation | Self-aligned and extended inter-well isolation structure |
-
2010
- 2010-01-12 US US12/685,998 patent/US8853091B2/en active Active
- 2010-01-13 WO PCT/US2010/020845 patent/WO2010083184A1/fr active Application Filing
- 2010-01-13 KR KR1020117007448A patent/KR101662218B1/ko active IP Right Grant
- 2010-01-13 EP EP10702178.4A patent/EP2387797B1/fr active Active
- 2010-01-13 CN CN201080004639.7A patent/CN102282666B/zh active Active
- 2010-01-15 TW TW099101133A patent/TWI476861B/zh active
-
2011
- 2011-03-21 IL IL211840A patent/IL211840A0/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020022327A1 (en) | 2000-08-16 | 2002-02-21 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a semiconductor device having an elevated source/drain scheme |
US20040029385A1 (en) | 2002-04-30 | 2004-02-12 | Dirk Manger | Semiconductor substrate with trenches of varying depth |
US20040092115A1 (en) | 2002-11-07 | 2004-05-13 | Winbond Electronics Corp. | Memory device having isolation trenches with different depths and the method for making the same |
Also Published As
Publication number | Publication date |
---|---|
US8853091B2 (en) | 2014-10-07 |
IL211840A0 (en) | 2011-06-30 |
EP2387797A1 (fr) | 2011-11-23 |
US20100184295A1 (en) | 2010-07-22 |
CN102282666B (zh) | 2014-12-17 |
CN102282666A (zh) | 2011-12-14 |
TW201036107A (en) | 2010-10-01 |
WO2010083184A1 (fr) | 2010-07-22 |
KR20110102872A (ko) | 2011-09-19 |
TWI476861B (zh) | 2015-03-11 |
EP2387797B1 (fr) | 2019-03-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101662218B1 (ko) | 다중 깊이 sti 방법 | |
KR100279016B1 (ko) | 반도체 제조시 비-컨포멀 디바이스 층을 평탄화하는 방법 | |
US7427552B2 (en) | Method for fabricating isolation structures for flash memory semiconductor devices | |
US8389400B2 (en) | Method of manufacturing fine patterns of semiconductor device | |
KR100741876B1 (ko) | 디보트가 방지된 트렌치 소자분리막이 형성된 반도체 소자의 제조 방법 | |
CN110896047A (zh) | 浅沟槽隔离结构和半导体器件的制备方法 | |
JP2004265989A (ja) | 半導体装置の製造方法 | |
CN111435658B (zh) | 形成存储器堆叠结构的方法 | |
US8361849B2 (en) | Method of fabricating semiconductor device | |
CN111384151B (zh) | 半导体基底及其制备方法 | |
CN108389830A (zh) | 掩模的制作方法 | |
KR100548571B1 (ko) | 반도체소자의 소자분리막 형성방법 | |
KR100700283B1 (ko) | 반도체소자의 소자분리용 트랜치 형성방법 | |
US20080160744A1 (en) | Method for fabricating semiconductor device and improving thin film uniformity | |
KR100712983B1 (ko) | 반도체 소자의 평탄화 방법 | |
KR100603249B1 (ko) | 플래시 메모리의 플로팅 게이트 형성방법 | |
CN113889433A (zh) | 半导体器件及其制备方法 | |
KR100508638B1 (ko) | 반도체 소자 제조 방법 | |
US7435642B2 (en) | Method of evaluating the uniformity of the thickness of the polysilicon gate layer | |
KR100578239B1 (ko) | 반도체장치의 소자분리막 형성방법 | |
CN116631938A (zh) | 半导体元件的制造方法 | |
KR20110076548A (ko) | 반도체 소자의 제조방법 | |
KR20050019616A (ko) | 집적 회로 소자 리세스 트랜지스터의 제조방법 및 이에의해 제조된 집적 회로 소자의 리세스 트랜지스터 | |
US20070148901A1 (en) | Method for manufacturing a semiconductor device | |
KR20020054666A (ko) | 반도체소자의 소자분리막 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant |