KR101423749B1 - 얇은 유전체 멤브레인을 사용한 쓰루-웨이퍼 전기적 상호연결 및 다른 구조들의 형성 - Google Patents

얇은 유전체 멤브레인을 사용한 쓰루-웨이퍼 전기적 상호연결 및 다른 구조들의 형성 Download PDF

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KR101423749B1
KR101423749B1 KR1020097006070A KR20097006070A KR101423749B1 KR 101423749 B1 KR101423749 B1 KR 101423749B1 KR 1020097006070 A KR1020097006070 A KR 1020097006070A KR 20097006070 A KR20097006070 A KR 20097006070A KR 101423749 B1 KR101423749 B1 KR 101423749B1
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wafer
metal
etch stop
membrane
delete delete
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KR20090076899A (ko
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리어 시브
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Pressure Sensors (AREA)
  • Micromachines (AREA)
  • Weting (AREA)
KR1020097006070A 2006-09-26 2007-09-25 얇은 유전체 멤브레인을 사용한 쓰루-웨이퍼 전기적 상호연결 및 다른 구조들의 형성 Expired - Fee Related KR101423749B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US84804306P 2006-09-26 2006-09-26
US60/848,043 2006-09-26
US11/669,664 US7531445B2 (en) 2006-09-26 2007-01-31 Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane
US11/669,664 2007-01-31
PCT/IB2007/004084 WO2008038158A2 (en) 2006-09-26 2007-09-25 Formation of through-wafer electrical interconnections and other structures using an etch stop layer

Publications (2)

Publication Number Publication Date
KR20090076899A KR20090076899A (ko) 2009-07-13
KR101423749B1 true KR101423749B1 (ko) 2014-08-01

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KR1020097006070A Expired - Fee Related KR101423749B1 (ko) 2006-09-26 2007-09-25 얇은 유전체 멤브레인을 사용한 쓰루-웨이퍼 전기적 상호연결 및 다른 구조들의 형성

Country Status (10)

Country Link
US (3) US7531445B2 (enExample)
EP (3) EP2082422B1 (enExample)
JP (1) JP5313903B2 (enExample)
KR (1) KR101423749B1 (enExample)
CN (1) CN101517729B (enExample)
DK (1) DK2082422T3 (enExample)
MY (1) MY145677A (enExample)
SG (1) SG177129A1 (enExample)
TW (1) TWI376016B (enExample)
WO (1) WO2008038158A2 (enExample)

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US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
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JP5584474B2 (ja) 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
CN101809739B (zh) 2007-07-27 2014-08-20 泰塞拉公司 具有后应用的衬垫延长部分的重构晶片堆封装
US8193615B2 (en) 2007-07-31 2012-06-05 DigitalOptics Corporation Europe Limited Semiconductor packaging process using through silicon vias
CN101861646B (zh) 2007-08-03 2015-03-18 泰塞拉公司 利用再生晶圆的堆叠封装
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8044755B2 (en) * 2008-04-09 2011-10-25 National Semiconductor Corporation MEMS power inductor
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
FR2938974B1 (fr) * 2008-11-25 2011-01-21 Tronic S Microsystems Composant microelectromecanique et procede de fabrication
US20100176507A1 (en) * 2009-01-14 2010-07-15 Hymite A/S Semiconductor-based submount with electrically conductive feed-throughs
US8309973B2 (en) 2009-02-12 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-based sub-mount for an opto-electronic device
US8729591B2 (en) 2009-02-13 2014-05-20 Tsmc Solid State Lighting Ltd. Opto-electronic device package with a semiconductor-based sub-mount having SMD metal contacts
KR101072143B1 (ko) * 2009-02-20 2011-10-10 엘지이노텍 주식회사 발광소자 패키지 및 그 제조방법
TWI446498B (zh) 2009-03-13 2014-07-21 泰斯拉公司 具有延伸穿越銲墊之通孔的堆疊微電子總成
US7838878B2 (en) * 2009-03-24 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-based sub-mounts for optoelectronic devices with conductive paths to facilitate testing and binning
US10500770B2 (en) * 2010-03-02 2019-12-10 So-Semi Technologies, Llc LED packaging with integrated optics and methods of manufacturing the same
JP2011204979A (ja) * 2010-03-26 2011-10-13 Oki Electric Industry Co Ltd 半導体チップ、半導体多層回路、及び、半導体チップの製造方法
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
CN102403413B (zh) * 2010-09-19 2013-09-18 常州普美电子科技有限公司 Led散热基板、led封装结构及二者的制作方法
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8617988B2 (en) * 2011-06-06 2013-12-31 Hewlett-Packard Development Company, L.P. Through-substrate vias
US8853072B2 (en) 2011-06-06 2014-10-07 Micron Technology, Inc. Methods of forming through-substrate interconnects
FR2985088B1 (fr) 2011-12-23 2015-04-17 Commissariat Energie Atomique Via tsv dote d'une structure de liberation de contraintes et son procede de fabrication
KR101284220B1 (ko) * 2012-07-06 2013-07-09 (주) 이피웍스 예각 반도체 웨이퍼를 사용한 관통 실리콘 비아 식각방법
JP5596773B2 (ja) * 2012-12-19 2014-09-24 日本電信電話株式会社 半導体装置の製造方法
US10319654B1 (en) 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
JP7112898B2 (ja) * 2018-06-27 2022-08-04 日産自動車株式会社 半導体装置及びその製造方法

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Also Published As

Publication number Publication date
HK1137565A1 (en) 2010-07-30
EP2750176A2 (en) 2014-07-02
US7531445B2 (en) 2009-05-12
SG177129A1 (en) 2012-01-30
WO2008038158A3 (en) 2008-08-28
TW200832615A (en) 2008-08-01
MY145677A (en) 2012-03-15
TWI376016B (en) 2012-11-01
US20080076195A1 (en) 2008-03-27
DK2082422T3 (en) 2014-12-08
US7732240B2 (en) 2010-06-08
WO2008038158B1 (en) 2008-11-27
US7662710B2 (en) 2010-02-16
JP2010505259A (ja) 2010-02-18
US20090191704A1 (en) 2009-07-30
JP5313903B2 (ja) 2013-10-09
KR20090076899A (ko) 2009-07-13
EP2750176A3 (en) 2014-07-16
EP2750177A3 (en) 2014-10-22
EP2750177A2 (en) 2014-07-02
WO2008038158A2 (en) 2008-04-03
CN101517729A (zh) 2009-08-26
US20100015734A1 (en) 2010-01-21
EP2082422B1 (en) 2014-11-26
CN101517729B (zh) 2011-08-10
EP2082422A2 (en) 2009-07-29

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