KR101237669B1 - 개재 굴곡 접착 요소를 갖는 다른 집적 회로 상에 하나의 집적 회로를 갖는 구조 - Google Patents

개재 굴곡 접착 요소를 갖는 다른 집적 회로 상에 하나의 집적 회로를 갖는 구조 Download PDF

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KR101237669B1
KR101237669B1 KR1020077023888A KR20077023888A KR101237669B1 KR 101237669 B1 KR101237669 B1 KR 101237669B1 KR 1020077023888 A KR1020077023888 A KR 1020077023888A KR 20077023888 A KR20077023888 A KR 20077023888A KR 101237669 B1 KR101237669 B1 KR 101237669B1
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semiconductor package
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lower substrate
semiconductor
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KR20080013864A (ko
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마크 에이. 맹그럼
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프리스케일 세미컨덕터, 인크.
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/40—Arrangements for protection of devices protecting against tampering, e.g. unauthorised inspection or reverse engineering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/657—Shapes or dispositions of interconnections on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

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  • Semiconductor Memories (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
KR1020077023888A 2005-04-18 2006-02-23 개재 굴곡 접착 요소를 갖는 다른 집적 회로 상에 하나의 집적 회로를 갖는 구조 Expired - Fee Related KR101237669B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/108,223 2005-04-18
US11/108,223 US7196427B2 (en) 2005-04-18 2005-04-18 Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element
PCT/US2006/006426 WO2006112949A2 (en) 2005-04-18 2006-02-23 Structure for stacking an integrated circuit on another integrated circuit

Publications (2)

Publication Number Publication Date
KR20080013864A KR20080013864A (ko) 2008-02-13
KR101237669B1 true KR101237669B1 (ko) 2013-02-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020077023888A Expired - Fee Related KR101237669B1 (ko) 2005-04-18 2006-02-23 개재 굴곡 접착 요소를 갖는 다른 집적 회로 상에 하나의 집적 회로를 갖는 구조

Country Status (5)

Country Link
US (1) US7196427B2 (https=)
EP (1) EP1875503A4 (https=)
JP (1) JP4768012B2 (https=)
KR (1) KR101237669B1 (https=)
WO (1) WO2006112949A2 (https=)

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US8299595B2 (en) * 2010-03-18 2012-10-30 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
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Also Published As

Publication number Publication date
EP1875503A4 (en) 2010-01-20
JP2008537333A (ja) 2008-09-11
WO2006112949A2 (en) 2006-10-26
US20060231938A1 (en) 2006-10-19
US7196427B2 (en) 2007-03-27
EP1875503A2 (en) 2008-01-09
JP4768012B2 (ja) 2011-09-07
KR20080013864A (ko) 2008-02-13
WO2006112949A3 (en) 2007-03-22

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