KR101218841B1 - 반도체 소자의 이동성 향상을 위한 방법 및 장치 - Google Patents
반도체 소자의 이동성 향상을 위한 방법 및 장치 Download PDFInfo
- Publication number
- KR101218841B1 KR101218841B1 KR1020077004357A KR20077004357A KR101218841B1 KR 101218841 B1 KR101218841 B1 KR 101218841B1 KR 1020077004357 A KR1020077004357 A KR 1020077004357A KR 20077004357 A KR20077004357 A KR 20077004357A KR 101218841 B1 KR101218841 B1 KR 101218841B1
- Authority
- KR
- South Korea
- Prior art keywords
- source
- substrate
- channel region
- semiconductor
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
- H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
- H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/925,108 US7288448B2 (en) | 2004-08-24 | 2004-08-24 | Method and apparatus for mobility enhancement in a semiconductor device |
| US10/925,108 | 2004-08-24 | ||
| PCT/US2005/026543 WO2006023219A2 (en) | 2004-08-24 | 2005-07-27 | Method and apparatus for mobility enhancement in a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20070046139A KR20070046139A (ko) | 2007-05-02 |
| KR101218841B1 true KR101218841B1 (ko) | 2013-01-21 |
Family
ID=35943818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020077004357A Expired - Lifetime KR101218841B1 (ko) | 2004-08-24 | 2005-07-27 | 반도체 소자의 이동성 향상을 위한 방법 및 장치 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US7288448B2 (https=) |
| EP (1) | EP1784854A2 (https=) |
| JP (1) | JP5060296B2 (https=) |
| KR (1) | KR101218841B1 (https=) |
| CN (1) | CN100533690C (https=) |
| TW (1) | TWI423342B (https=) |
| WO (1) | WO2006023219A2 (https=) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100642747B1 (ko) * | 2004-06-22 | 2006-11-10 | 삼성전자주식회사 | Cmos 트랜지스터의 제조방법 및 그에 의해 제조된cmos 트랜지스터 |
| JP4327104B2 (ja) * | 2005-01-20 | 2009-09-09 | 富士通マイクロエレクトロニクス株式会社 | Mos型電界効果トランジスタの製造方法及びmos型電界効果トランジスタ |
| US20080121932A1 (en) | 2006-09-18 | 2008-05-29 | Pushkar Ranade | Active regions with compatible dielectric layers |
| US7470972B2 (en) * | 2005-03-11 | 2008-12-30 | Intel Corporation | Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress |
| US7429775B1 (en) * | 2005-03-31 | 2008-09-30 | Xilinx, Inc. | Method of fabricating strain-silicon CMOS |
| US7446350B2 (en) * | 2005-05-10 | 2008-11-04 | International Business Machine Corporation | Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer |
| US7423283B1 (en) | 2005-06-07 | 2008-09-09 | Xilinx, Inc. | Strain-silicon CMOS using etch-stop layer and method of manufacture |
| US7655991B1 (en) | 2005-09-08 | 2010-02-02 | Xilinx, Inc. | CMOS device with stressed sidewall spacers |
| US7936006B1 (en) | 2005-10-06 | 2011-05-03 | Xilinx, Inc. | Semiconductor device with backfilled isolation |
| JP2007157788A (ja) * | 2005-11-30 | 2007-06-21 | Toshiba Corp | 半導体装置 |
| US7479422B2 (en) * | 2006-03-10 | 2009-01-20 | Freescale Semiconductor, Inc. | Semiconductor device with stressors and method therefor |
| US7279758B1 (en) * | 2006-05-24 | 2007-10-09 | International Business Machines Corporation | N-channel MOSFETs comprising dual stressors, and methods for forming the same |
| DE102006035669B4 (de) * | 2006-07-31 | 2014-07-10 | Globalfoundries Inc. | Transistor mit einem verformten Kanalgebiet, das eine leistungssteigernde Materialzusammensetzung aufweist und Verfahren zur Herstellung |
| US7897493B2 (en) * | 2006-12-08 | 2011-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inducement of strain in a semiconductor layer |
| US8003454B2 (en) * | 2008-05-22 | 2011-08-23 | Freescale Semiconductor, Inc. | CMOS process with optimized PMOS and NMOS transistor devices |
| US20090289280A1 (en) * | 2008-05-22 | 2009-11-26 | Da Zhang | Method for Making Transistors and the Device Thereof |
| JP5295651B2 (ja) * | 2008-06-13 | 2013-09-18 | 株式会社東芝 | 乱数生成装置 |
| US8299453B2 (en) * | 2009-03-03 | 2012-10-30 | International Business Machines Corporation | CMOS transistors with silicon germanium channel and dual embedded stressors |
| US20110049582A1 (en) * | 2009-09-03 | 2011-03-03 | International Business Machines Corporation | Asymmetric source and drain stressor regions |
| US8035141B2 (en) * | 2009-10-28 | 2011-10-11 | International Business Machines Corporation | Bi-layer nFET embedded stressor element and integration to enhance drive current |
| KR101576529B1 (ko) * | 2010-02-12 | 2015-12-11 | 삼성전자주식회사 | 습식 식각을 이용한 실리콘 파셋트를 갖는 반도체 장치 및 제조방법 |
| US8962417B2 (en) | 2010-10-15 | 2015-02-24 | International Business Machines Corporation | Method and structure for pFET junction profile with SiGe channel |
| US8659054B2 (en) * | 2010-10-15 | 2014-02-25 | International Business Machines Corporation | Method and structure for pFET junction profile with SiGe channel |
| CN103367430B (zh) * | 2012-03-29 | 2016-11-02 | 中芯国际集成电路制造(上海)有限公司 | 晶体管以及形成方法 |
| KR20150020845A (ko) * | 2013-08-19 | 2015-02-27 | 에스케이하이닉스 주식회사 | 수직 채널을 갖는 반도체 장치, 그를 포함하는 저항 변화 메모리 장치 및 그 제조방법 |
| FR3011119B1 (fr) * | 2013-09-23 | 2017-09-29 | Commissariat Energie Atomique | Procede de realisation d'un transistor |
| FR3023411B1 (fr) * | 2014-07-07 | 2017-12-22 | Commissariat Energie Atomique | Generation localisee de contrainte dans un substrat soi |
| CN105244281A (zh) * | 2015-10-14 | 2016-01-13 | 上海华力微电子有限公司 | 一种半导体器件的制备方法 |
| FR3087658B1 (fr) | 2018-10-26 | 2021-09-17 | Basf Beauty Care Solutions France Sas | Nouvelles utilisations cosmetiques et dermatologiques d'un extrait du champignon inonotus obliquus |
| CN118825064B (zh) * | 2024-09-03 | 2025-02-18 | 深圳平湖实验室 | 半导体器件及其制备方法、芯片、电子设备 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010028838A (ko) * | 1999-09-27 | 2001-04-06 | 윤종용 | SiGe 채널의 모스 트랜지스터 및 그 제조 방법 |
| US20030080361A1 (en) * | 2001-11-01 | 2003-05-01 | Anand Murthy | Semiconductor transistor having a stressed channel |
| US20030102490A1 (en) * | 2000-12-26 | 2003-06-05 | Minoru Kubo | Semiconductor device and its manufacturing method |
| KR20040007256A (ko) * | 2002-07-11 | 2004-01-24 | 샤프 가부시키가이샤 | 실리콘 기판 상에 Si₁-xGex 막을 제조하는 방법 |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3146045B2 (ja) * | 1992-01-06 | 2001-03-12 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US5789306A (en) * | 1996-04-18 | 1998-08-04 | Micron Technology, Inc. | Dual-masked field isolation |
| US5849440A (en) * | 1996-07-02 | 1998-12-15 | Motorola, Inc. | Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same |
| JP3311940B2 (ja) * | 1996-09-17 | 2002-08-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US5891769A (en) * | 1997-04-07 | 1999-04-06 | Motorola, Inc. | Method for forming a semiconductor device having a heteroepitaxial layer |
| US5858830A (en) * | 1997-06-12 | 1999-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making dual isolation regions for logic and embedded memory devices |
| JPH11163343A (ja) * | 1997-11-28 | 1999-06-18 | Nec Corp | 半導体装置およびその製造方法 |
| JP3443343B2 (ja) * | 1997-12-03 | 2003-09-02 | 松下電器産業株式会社 | 半導体装置 |
| US6197632B1 (en) * | 1999-11-16 | 2001-03-06 | International Business Machines Corporation | Method for dual sidewall oxidation in high density, high performance DRAMS |
| JP3420168B2 (ja) * | 2000-04-07 | 2003-06-23 | 株式会社東芝 | 電界効果トランジスタ及びこれを用いた集積化論理回路 |
| US6541382B1 (en) * | 2000-04-17 | 2003-04-01 | Taiwan Semiconductor Manufacturing Company | Lining and corner rounding method for shallow trench isolation |
| US6319799B1 (en) * | 2000-05-09 | 2001-11-20 | Board Of Regents, The University Of Texas System | High mobility heterojunction transistor and method |
| JP2001338988A (ja) * | 2000-05-25 | 2001-12-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
| US7312485B2 (en) | 2000-11-29 | 2007-12-25 | Intel Corporation | CMOS fabrication process utilizing special transistor orientation |
| JP3618319B2 (ja) * | 2000-12-26 | 2005-02-09 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
| JP4034627B2 (ja) * | 2001-09-28 | 2008-01-16 | テキサス インスツルメンツ インコーポレイテツド | 集積回路及びその製造方法 |
| US6600170B1 (en) * | 2001-12-17 | 2003-07-29 | Advanced Micro Devices, Inc. | CMOS with strained silicon channel NMOS and silicon germanium channel PMOS |
| US6605498B1 (en) * | 2002-03-29 | 2003-08-12 | Intel Corporation | Semiconductor transistor having a backfilled channel material |
| JP2004079887A (ja) * | 2002-08-21 | 2004-03-11 | Renesas Technology Corp | 半導体装置 |
| US6787864B2 (en) * | 2002-09-30 | 2004-09-07 | Advanced Micro Devices, Inc. | Mosfets incorporating nickel germanosilicided gate and methods for their formation |
| JP2004193203A (ja) * | 2002-12-09 | 2004-07-08 | Matsushita Electric Ind Co Ltd | 電界効果トランジスタおよびその製造方法 |
| JP2004200335A (ja) * | 2002-12-18 | 2004-07-15 | Toshiba Corp | 絶縁ゲート型電界効果トランジスタを含む半導体装置及びその製造方法 |
| JP4301816B2 (ja) * | 2003-01-06 | 2009-07-22 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
| US7019326B2 (en) * | 2003-11-14 | 2006-03-28 | Intel Corporation | Transistor with strain-inducing structure in channel |
| US7227205B2 (en) * | 2004-06-24 | 2007-06-05 | International Business Machines Corporation | Strained-silicon CMOS device and method |
| US7413957B2 (en) * | 2004-06-24 | 2008-08-19 | Applied Materials, Inc. | Methods for forming a transistor |
| US7470972B2 (en) * | 2005-03-11 | 2008-12-30 | Intel Corporation | Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress |
-
2004
- 2004-08-24 US US10/925,108 patent/US7288448B2/en not_active Expired - Lifetime
-
2005
- 2005-07-27 JP JP2007529871A patent/JP5060296B2/ja not_active Expired - Lifetime
- 2005-07-27 EP EP05776548A patent/EP1784854A2/en not_active Withdrawn
- 2005-07-27 CN CNB2005800248608A patent/CN100533690C/zh not_active Expired - Lifetime
- 2005-07-27 KR KR1020077004357A patent/KR101218841B1/ko not_active Expired - Lifetime
- 2005-07-27 WO PCT/US2005/026543 patent/WO2006023219A2/en not_active Ceased
- 2005-08-09 TW TW094127044A patent/TWI423342B/zh not_active IP Right Cessation
-
2007
- 2007-09-18 US US11/857,122 patent/US7872311B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010028838A (ko) * | 1999-09-27 | 2001-04-06 | 윤종용 | SiGe 채널의 모스 트랜지스터 및 그 제조 방법 |
| US20030102490A1 (en) * | 2000-12-26 | 2003-06-05 | Minoru Kubo | Semiconductor device and its manufacturing method |
| US20030080361A1 (en) * | 2001-11-01 | 2003-05-01 | Anand Murthy | Semiconductor transistor having a stressed channel |
| KR20040007256A (ko) * | 2002-07-11 | 2004-01-24 | 샤프 가부시키가이샤 | 실리콘 기판 상에 Si₁-xGex 막을 제조하는 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1989602A (zh) | 2007-06-27 |
| WO2006023219A3 (en) | 2006-09-28 |
| JP2008511173A (ja) | 2008-04-10 |
| WO2006023219A2 (en) | 2006-03-02 |
| US7288448B2 (en) | 2007-10-30 |
| US20080006880A1 (en) | 2008-01-10 |
| EP1784854A2 (en) | 2007-05-16 |
| TWI423342B (zh) | 2014-01-11 |
| JP5060296B2 (ja) | 2012-10-31 |
| CN100533690C (zh) | 2009-08-26 |
| US20060046366A1 (en) | 2006-03-02 |
| TW200629419A (en) | 2006-08-16 |
| US7872311B2 (en) | 2011-01-18 |
| KR20070046139A (ko) | 2007-05-02 |
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