KR101195886B1 - 배선 기판의 제조 방법 및 반도체 장치의 제조 방법 - Google Patents

배선 기판의 제조 방법 및 반도체 장치의 제조 방법 Download PDF

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Publication number
KR101195886B1
KR101195886B1 KR1020060104331A KR20060104331A KR101195886B1 KR 101195886 B1 KR101195886 B1 KR 101195886B1 KR 1020060104331 A KR1020060104331 A KR 1020060104331A KR 20060104331 A KR20060104331 A KR 20060104331A KR 101195886 B1 KR101195886 B1 KR 101195886B1
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KR
South Korea
Prior art keywords
layer
semiconductor chip
pattern
wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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KR1020060104331A
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English (en)
Korean (ko)
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KR20070049957A (ko
Inventor
기요시 오이
Original Assignee
신꼬오덴기 고교 가부시키가이샤
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Application filed by 신꼬오덴기 고교 가부시키가이샤 filed Critical 신꼬오덴기 고교 가부시키가이샤
Publication of KR20070049957A publication Critical patent/KR20070049957A/ko
Application granted granted Critical
Publication of KR101195886B1 publication Critical patent/KR101195886B1/ko
Expired - Fee Related legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/243—Reinforcing of the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0361—Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
KR1020060104331A 2005-11-09 2006-10-26 배선 기판의 제조 방법 및 반도체 장치의 제조 방법 Expired - Fee Related KR101195886B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2005-00325090 2005-11-09
JP2005325090A JP4718305B2 (ja) 2005-11-09 2005-11-09 配線基板の製造方法および半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR20070049957A KR20070049957A (ko) 2007-05-14
KR101195886B1 true KR101195886B1 (ko) 2012-10-30

Family

ID=38041418

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060104331A Expired - Fee Related KR101195886B1 (ko) 2005-11-09 2006-10-26 배선 기판의 제조 방법 및 반도체 장치의 제조 방법

Country Status (4)

Country Link
US (1) US20070111387A1 (https=)
JP (1) JP4718305B2 (https=)
KR (1) KR101195886B1 (https=)
TW (1) TW200731436A (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI434405B (zh) * 2011-06-07 2014-04-11 國立交通大學 具有積體電路與發光二極體之異質整合結構及其製作方法
US20150195912A1 (en) * 2014-01-08 2015-07-09 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Substrates With Ultra Fine Pitch Flip Chip Bumps
US9642261B2 (en) * 2014-01-24 2017-05-02 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Composite electronic structure with partially exposed and protruding copper termination posts
JP6502814B2 (ja) * 2015-09-25 2019-04-17 京セラ株式会社 指紋センサー用配線基板
JP2017063163A (ja) * 2015-09-25 2017-03-30 京セラ株式会社 指紋センサー用配線基板

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1056253A (ja) 1996-08-09 1998-02-24 Matsushita Electric Works Ltd 独立回路へのメッキ方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0245996A (ja) * 1988-08-05 1990-02-15 Nec Corp 混成集積回路の製造方法
JPH02162734A (ja) * 1988-12-16 1990-06-22 Fujitsu Ltd 半導体装置の製造方法
JPH03129831A (ja) * 1989-10-16 1991-06-03 Nec Corp 半導体装置の製造方法
JPH03139851A (ja) * 1989-10-25 1991-06-14 Aoi Denshi Kk 半導体装置
JP3003394B2 (ja) * 1992-06-24 2000-01-24 松下電器産業株式会社 突起電極の製造方法
JPH0964493A (ja) * 1995-08-29 1997-03-07 Nippon Mektron Ltd 回路基板の配線構造及びその形成法
JP2002009203A (ja) * 2000-06-23 2002-01-11 Dainippon Printing Co Ltd 配線形成方法と配線基板
JP4480111B2 (ja) * 2000-08-02 2010-06-16 大日本印刷株式会社 配線形成方法および配線部材
US6890829B2 (en) * 2000-10-24 2005-05-10 Intel Corporation Fabrication of on-package and on-chip structure using build-up layer process
JP2002141437A (ja) * 2000-11-06 2002-05-17 Dainippon Printing Co Ltd Ｃｓｐタイプの半導体装置及びその作製方法
JP2002170845A (ja) * 2000-12-04 2002-06-14 Sumitomo Bakelite Co Ltd 半導体装置の製造方法および半導体装置
JP2002246744A (ja) * 2001-02-20 2002-08-30 Nec Corp 導体形成方法およびこれを用いた多層配線基板製造方法
US6660633B1 (en) * 2002-02-26 2003-12-09 Advanced Micro Devices, Inc. Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed
DE10355953B4 (de) * 2003-11-29 2005-10-20 Infineon Technologies Ag Verfahren zum Galvanisieren und Kontaktvorsprungsanordnung
KR100597993B1 (ko) * 2004-04-08 2006-07-10 주식회사 네패스 반도체 패키지용 범프, 그 범프를 적용한 반도체 패키지 및 제조방법
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US7179738B2 (en) * 2004-06-17 2007-02-20 Texas Instruments Incorporated Semiconductor assembly having substrate with electroplated contact pads

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1056253A (ja) 1996-08-09 1998-02-24 Matsushita Electric Works Ltd 独立回路へのメッキ方法

Also Published As

Publication number Publication date
JP2007134458A (ja) 2007-05-31
KR20070049957A (ko) 2007-05-14
JP4718305B2 (ja) 2011-07-06
US20070111387A1 (en) 2007-05-17
TW200731436A (en) 2007-08-16

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