TWI434405B - 具有積體電路與發光二極體之異質整合結構及其製作方法 - Google Patents

具有積體電路與發光二極體之異質整合結構及其製作方法 Download PDF

Info

Publication number
TWI434405B
TWI434405B TW100119755A TW100119755A TWI434405B TW I434405 B TWI434405 B TW I434405B TW 100119755 A TW100119755 A TW 100119755A TW 100119755 A TW100119755 A TW 100119755A TW I434405 B TWI434405 B TW I434405B
Authority
TW
Taiwan
Prior art keywords
block
emitting diode
conductive
integrated circuit
light emitting
Prior art date
Application number
TW100119755A
Other languages
English (en)
Other versions
TW201250997A (en
Inventor
Kuan Neng Chen
Cheng Ta Ko
Wei Chung Lo
Original Assignee
Univ Nat Chiao Tung
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Nat Chiao Tung filed Critical Univ Nat Chiao Tung
Priority to TW100119755A priority Critical patent/TWI434405B/zh
Priority to CN2011101922135A priority patent/CN102263097A/zh
Priority to JP2011163255A priority patent/JP2012256810A/ja
Priority to KR1020110087639A priority patent/KR101259308B1/ko
Priority to US13/224,607 priority patent/US8536613B2/en
Publication of TW201250997A publication Critical patent/TW201250997A/zh
Priority to US14/019,933 priority patent/US8679891B2/en
Application granted granted Critical
Publication of TWI434405B publication Critical patent/TWI434405B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
    • H01L2224/0362—Photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1161—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/145—Material
    • H01L2224/14505—Bump connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Description

具有積體電路與發光二極體之異質整合結構及其製作方法
本發明係有關一種異質整合技術，特別是關於一種具有積體電路與發光二極體之異質整合結構及其製作方法。
發光二極體(Light Emitting Diode,LED)是一種冷光發光元件，其係利用半導體材料中電子電洞結合所釋放出的能量，以光的形式釋出。依據使用材料的不同，其可發出不同波長的單色光。主要可區分為可見光發光二極體與不可見光(紅外線)發光二極體兩種，由於發光二極體相較於傳統燈泡發光的形式，具有省電、耐震及閃爍速度快等優點，因此成為日常生活中不可或缺的重要元件。
先前技術之製作具散熱效果之發光二極體之各步驟結構剖視圖，如第1(a)圖至第1(c)圖所示，如第1(a)圖所示，首先於藍寶石基板10上沈積製作發光二極體12，接著如第1(b)圖所示，再利用金屬接著(metal adhesive)層14與高熱傳導之矽基板16進行接合，最後如第1(c)圖所示，再將藍寶石基板10進行移除。在此發光二極體12與矽基板16之接合，主要在於利用高熱傳導之矽基板16幫助散熱，發光二極體12與矽基板16間並無任何電性連接功效，而接合方式上乃利用整層的金屬接著層14進行接合，以助於發光二極體12產生的熱可向下傳導至矽基板16順利散熱。雖然以往的技術有利用矽基板16來散熱，但發光二極體12之製作主要仍為高溫製程，對於高熱預算(thermal budget)與熱應力的產生，亦無法免除。此外，此種發光二極體並未與功能性積體電路整合。
因此，本發明係在針對上述之困擾，提出一種具有積體電路與發光二極體之異質整合結構及其製作方法，以解決習知所產生的問題。
本發明之主要目的，在於提供一種具有積體電路與發光二極體之異質整合結構及其製作方法，其係利用金屬與接合塊之混合型接合(hybrid bonding)方式將積體電路與發光二極體做堆疊連接，使積體電路與發光二極體之間除了有散熱功能外，更有電訊上之連接功用，以達到高密度、多功能之異質整合技術開發與應用。
為達上述目的，本發明提供一種具有積體電路與發光二極體之異質整合結構，包含一積體電路，其表面設有至少一接合結構與至少一導電結構，以與導電結構電性連接。另有一發光二極體，其具相異兩側之一第一面及第二面，發光二極體之第一面位於接合結構與導電結構上，以與積體電路相結合，且使發光二極體電性連接導電結構。此外，更可於發光二極體中設有一導電通孔，以與導電結構電性連接，且上述之第二面亦設有一導電塊，以與導電通孔電性連接，進而利於在發光二極體上堆疊其餘應用結構。
本發明亦提供一種具有積體電路與發光二極體之異質整合結構之製作方法，首先，提供一積體電路與一發光二極體，積體電路之表面設有至少一第一導電塊與至少一第一接合塊，以與第一導電塊電性連接，發光二極體具有相異兩側之一第一、第二面，第一面設有至少一第二導電塊與至少一第二接合塊，以與第二導電塊電性連接。接著，積體電路將第一導電塊與第一接合塊分別與第二導電塊與第二接合塊對應接合，以與發光二極體相結合，並使第一、第二導電塊電性連接。更者，發光二極體中更設有與導電結構連接之一導電通孔，且第二面設有一導電塊，與導電通孔電性連接。當積體電路與發光二極體結合時，便形成一易於發光二極體上堆疊之異質整合結構。
茲為使　貴審查委員對本發明之結構特徵及所達成之功效更有進一步之瞭解與認識，謹佐以較佳之實施例圖及配合詳細之說明，說明如後：
以下先介紹本發明之第一實施例，請參閱第2圖。本發明包含一積體電路18，其表面設有至少一接合結構20與至少一導電結構22，並使積體電路18與導電結構22電性連接。另有一發光二極體24，其具相異兩側之一第一面及第二面，發光二極體24之第一面位於接合結構20與導電結構22上，以與積體電路18相結合，且使發光二極體24電性連接導電結構22。在上述結構中，積體電路18具多功能，例如可提供發光二極體24電源，或作為邏輯控制處理器、記憶體、互補式金氧半(CMOS)影像感測器、射頻積體電路等功能。相對於先前技術，本發明將矽基板以積體電路18來取代，因此在本發明中，積體電路18與發光二極體24之間除了散熱外，更有電訊上之連接，以達到高密度及多功能之異質整合技術開發與應用。
在接合結構20中，更包含一第一、第二接合塊26、28，其材質可選用如適用於攝氏250度以下之環氧樹脂基光阻(SU-8)之高分子材料，第一接合塊係設於積體電路18之表面上，第二接合塊28則設於發光二極體24之第一面上，並與第一接合塊26相接合。導電結構22更包含材質為金屬之一第一導電塊與一第二導電塊30，第一導電塊係設於積體電路18之表面上，以與積體電路18電性連接，第二導電塊30係設於發光二極體24之第一面上，以與發光二極體24電性連接，且第二導電塊30與第一導電塊相接合，並電性連接之。第一導電塊包含二結構，其一為高溫接合金屬塊32，其係設於積體電路18之表面上，以與積體電路18電性連接，另一為低溫接合金屬塊34，其係接合高溫接合金屬塊32與第二導電塊30，以電性連接之。其中低溫接合金屬塊34之材質可選用如適用於攝氏250度以下之錫(Sn)或銦(In)等之金屬材料。換言之，積體電路18與發光二極體24之連接係採用金屬及高分子材料混合型接合(hybrid bonding)方式，其中金屬部份提供電訊連接，高分子部份則提供結構補強，其技術特點為金屬及高分子皆為接合材料，藉此，同時達到積體電路18與發光二極體24之電性連接及微間距高分子填充的效果，進而增加積體電路18與發光二極體24之接合強度及堆疊元件使用上的可靠性。
以下介紹第一實施例之製作方法，請參閱第3(a)圖至第3(d)圖。首先，如第3(a)圖所示，先形成高溫接合金屬塊32於積體電路18之表面上，使高溫接合金屬塊32與積體電路18電性連接，再形成低溫接合金屬塊34於高溫接合金屬塊32上，以與高溫接合金屬塊32電性連接，此高溫接合金屬塊32與低溫接合金屬塊34便可構成第一導電塊36。同時，形成第二導電塊30於發光二極體24之第一面上，以與發光二極體24電性連接，其中，形成高溫接合金屬塊32、低溫接合金屬塊34與第二導電塊30係以光微影、電鍍及蝕刻製程進行。接著，如第3(b)圖所示，分別形成第一、第二接合塊26、28於積體電路18之表面與發光二極體24之第一面，且形成方式係以光微影製程進行之。再來，如第3(c)圖所示，由於發光二極體24較適合低溫製程，且接合及導電材料亦允許低溫製程，因此可對第一、第二接合塊26、28與第一、第二導電塊30、36施以攝氏250～25度之低溫，使積體電路18將第一導電塊36之低溫接合金屬塊34與第一接合塊26分別與第二導電塊30與第二接合塊28對應接合，以與發光二極體24相結合，並使低溫接合金屬塊34、第二導電塊30電性連接，完成低溫接合之異質整合結構38。最後，如第3(d)圖所示，更可執行一切割步驟，其係對積體電路18及發光二極體24構成之異質整合結構38進行切割，如利用第3(c)圖中的虛線，以成為複數異質整合單元40。
在上述流程中，第3(d)圖之步驟可以省略。此外，在第3(a)圖之步驟中，其中形成高溫接合金屬塊32與低溫接合金屬塊34於積體電路18上之步驟，更可用直接形成包含高溫接合金屬塊32與低溫接合金屬塊34之第一導電塊36於積體電路18之表面上之步驟來取代，其中必須使高溫接合金屬塊32位於低溫接合金屬塊34與積體電路18之間。還有，在第3(a)圖至第3(c)圖之流程中，第3(a)圖與第3(b)圖之步驟，可以用單一步驟取代之，即直接提供積體電路18與發光二極體24，且積體電路18之表面設有至少一第一導電塊36與至少一第一接合塊26，以與第一導電塊36電性連接，發光二極體24具有相異兩側之第一、第二面，第一面設有至少一第二導電塊30與至少一第二接合塊28，以與第二導電塊30電性連接，其表示圖示與第3(b)圖相同。接著，再進行第3(c)圖之步驟。
以下介紹本發明之第二實施例，請參閱第4圖。第二實施例與第一實施例差別僅在於，第二實施例之發光二極體24更設有至少一導電通孔42，其係與導電結構22之第二導電塊30電性連接，且發光二極體24之第二面更設有材質為金屬之至少一第三導電塊44，其係與導電通孔42電性連接。
以下介紹第二實施例之製作方法，請參閱第5(a)圖至第5(e)圖。首先，如第5(a)圖所示，先形成高溫接合金屬塊32於積體電路18之表面上，使高溫接合金屬塊32與積體電路18電性連接，再形成低溫接合金屬塊34於高溫接合金屬塊32上，以與高溫接合金屬塊32電性連接，此高溫接合金屬塊32與低溫接合金屬塊34便可構成第一導電塊36。同時，形成第二導電塊30於發光二極體24之第一面上，以與發光二極體24電性連接，其中，形成高溫接合金屬塊32、低溫接合金屬塊34與第二導電塊30係以光微影、電鍍及蝕刻製程進行。接著，如第5(b)圖所示，先形成導電通孔42於發光二極體24中，以與第二導電塊30電性連接。接續之，以光微影、電鍍及蝕刻製程，形成第三導電塊44於發光二極體24之第二面，並與導電通孔42電性連接，以利於發光二極體24安裝或堆疊其他元件。再來，如第5(c)圖所示，分別形成第一、第二接合塊26、28於積體電路18之表面與發光二極體24之第一面，且形成方式係以光微影製程進行之。接著，如第5(d)圖所示，與第一實施例的方式類似，對第一、第二接合塊26、28與第一、第二導電塊36、30施以攝氏250～25度之低溫，使積體電路18將第一導電塊36之低溫接合金屬塊34與第一接合塊26分別與第二導電塊30與第二接合塊28對應接合，以與發光二極體24相結合，並使低溫接合金屬塊34、第二導電塊30電性連接，完成低溫接合之異質整合結構46。最後，如第5(e)圖所示，更可執行一切割步驟，其係對積體電路18及發光二極體24構成之異質整合結構46進行切割，如利用第5(d)圖中的虛線，以成為複數異質整合單元48。
在上述流程中，第5(e)圖之步驟可以省略。此外，在第5(a)圖之步驟中，其中形成高溫接合金屬塊32與低溫接合金屬塊34於積體電路18上之步驟，更可用直接形成包含高溫接合金屬塊32與低溫接合金屬塊34之第一導電塊36於積體電路18之表面上之步驟來取代，其中必須使高溫接合金屬塊32位於低溫接合金屬塊34與積體電路18之間。還有，在第5(a)圖至第5(d)圖之流程中，第5(a)圖至第5(c)圖之步驟，可以用單一步驟取代之，即直接提供積體電路18與發光二極體24，且積體電路18之表面設有至少一第一導電塊36與至少一第一接合塊26，以與第一導電塊36電性連接，發光二極體24具有相異兩側之第一、第二面，第一面設有至少一第二導電塊30與至少一第二接合塊28，以與第二導電塊30電性連接，發光二極體24更設有至少一導電通孔42，其係與第二導電塊30電性連接，且發光二極體24之第二面更設有至少一第三導電塊44，其係與導電通孔42電性連接，其表示圖示與第5(c)圖相同。接著，再進行第5(d)圖之步驟。
綜上所述，本發明不但具有散熱功能，更有電訊上之連接功用，可應用於高密度、多功能之異質整合技術。
以上所述者，僅為本發明一較佳實施例而已，並非用來限定本發明實施之範圍，故舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。
10．．．藍寶石基板
12．．．發光二極體
14．．．金屬接著層
16．．．矽基板
18．．．積體電路
20．．．接合結構
22．．．導電結構
24．．．發光二極體
26．．．第一接合塊
28．．．第二接合塊
30．．．第二導電塊
32．．．高溫接合金屬塊
34．．．低溫接合金屬塊
36．．．第一導電塊
38．．．異質整合結構
40．．．異質整合單元
42．．．導電通孔
44．．．第三導電塊
46．．．異質整合結構
48．．．異質整合單元
第1(a)圖至第1(c)圖為先前技術之製作具散熱效果之發光二極體之各步驟結構剖視圖。
第2圖為本發明之第一實施例之結構剖視圖。
第3(a)圖至第3(c)圖為本發明之製作第一實施例之各步驟結構剖視圖。
第3(d)圖為本發明之第一實施例進行切割步驟示意圖。
第4圖為本發明之第二實施例之結構剖視圖。
第5(a)圖至第5(d)圖為本發明之製作第二實施例之各步驟結構剖視圖。
第5(e)圖為本發明之第二實施例進行切割步驟示意圖。
18．．．積體電路
20．．．接合結構
22．．．導電結構
24．．．發光二極體
26．．．第一接合塊
28．．．第二接合塊
30．．．第二導電塊
32．．．高溫接合金屬塊
34．．．低溫接合金屬塊

Claims (19)

  1. 一種具有積體電路與發光二極體之異質整合結構，包括：一積體電路；至少一接合結構，其係設於該積體電路之表面；至少一導電結構，其係設於該表面，並與該積體電路電性連接；以及一發光二極體，其具相異兩側之一第一面及第二面，該發光二極體之該第一面位於該接合結構與該導電結構上，以與該積體電路相結合，且使該發光二極體電性連接該導電結構，該發光二極體更設有至少一導電通孔，其係與該導電結構電性連接，且該第二面更設有至少一第三導電塊，其係與該導電通孔電性連接。
  2. 如請求項1所述之具有積體電路與發光二極體之異質整合結構，其中該接合結構更包含：一第一接合塊，其係設於該表面上；以及一第二接合塊，其係設於該第一面上，並與該第一接合塊相接合。
  3. 如請求項2所述之具有積體電路與發光二極體之異質整合結構，其中該第一、第二接合塊之材質為環氧樹脂基光阻(SU-8)。
  4. 如請求項1所述之具有積體電路與發光二極體之異質整合結構，其中該導電結構更包含：一第一導電塊，其係設於該表面上，以與該積體電路電性連接；以及一第二導電塊，其係設於該第一面上，以與該發光二極體電性連接，且該第二導電塊與該第一導電塊相接合，並電性連接之。
  5. 如請求項4所述之具有積體電路與發光二極體之異質整合結構，其中該 第一、第二導電塊為金屬材質。
  6. 如請求項4所述之具有積體電路與發光二極體之異質整合結構，其中該第一導電塊更包含：一高溫接合金屬塊，其係設於該表面上，以與該積體電路電性連接；以及一低溫接合金屬塊，其係接合該高溫接合金屬塊與該第二導電塊，以電性連接之。
  7. 如請求項6所述之具有積體電路與發光二極體之異質整合結構，其中該低溫接合金屬塊之材質為錫(Sn)或銦(In)。
  8. 如請求項1所述之具有積體電路與發光二極體之異質整合結構，其中該第三導電塊為金屬材質。
  9. 一種具有積體電路與發光二極體之異質整合結構之製作方法，包括下列步驟：提供一積體電路與一發光二極體，該積體電路之表面設有至少一第一導電塊與至少一第一接合塊，以與該第一導電塊電性連接，該發光二極體具有相異兩側之一第一、第二面，該第一面設有至少一第二導電塊與至少一第二接合塊，以與該第二導電塊電性連接；以及該積體電路將該第一導電塊與該第一接合塊分別與該第二導電塊與該第二接合塊對應接合，以與該發光二極體相結合，並使該第一、第二導電塊電性連接。
  10. 如請求項9所述之具有積體電路與發光二極體之異質整合結構之製作方法，其中提供設有該第一導電塊與該第一接合塊之該積體電路之步驟更 包含下列步驟：形成該第一導電塊於該表面，以與該積體電路電性連接；以及形成該第一接合塊於該表面。
  11. 如請求項10所述之具有積體電路與發光二極體之異質整合結構之製作方法，其中形成該第一導電塊係以光微影、電鍍及蝕刻製程進行，形成該第一接合塊係以光微影製程進行。
  12. 如請求項10所述之具有積體電路與發光二極體之異質整合結構之製作方法，其中形成該第一導電塊於該表面上之步驟更包含下列步驟：形成一高溫接合金屬塊於該表面上，以與該積體電路電性連接；以及形成一低溫接合金屬塊於該高溫接合金屬塊上，以與該高溫接合金屬塊電性連接。
  13. 如請求項9所述之具有積體電路與發光二極體之異質整合結構之製作方法，其中提供設有該第二導電塊與該第二接合塊之該發光二極體之步驟更包含下列步驟：形成該第二導電塊於該第一面，以與該發光二極體電性連接；以及形成該第二接合塊於該第一面。
  14. 如請求項13所述之具有積體電路與發光二極體之異質整合結構之製作方法，其中形成該第二導電塊係以光微影、電鍍及蝕刻製程進行，形成該第二接合塊係以光微影製程進行。
  15. 如請求項9所述之具有積體電路與發光二極體之異質整合結構之製作方法，其中該積體電路與該發光二極體相結合之步驟中，係對該第一、第二接合塊與該第一第二導電塊施以攝氏250~25度，以進行低溫接合。
  16. 如請求項9所述之具有積體電路與發光二極體之異質整合結構之製作方法，其中提供設有該第二導電塊與該第二接合塊之該發光二極體之步驟中，該發光二極體更設有至少一導電通孔，其係與該第二導電塊電性連接，且該第二面更設有至少一第三導電塊，其係與該導電通孔電性連接。
  17. 如請求項16所述之具有積體電路與發光二極體之異質整合結構之製作方法，其中提供設有該第二導電塊、該第二接合塊、該導電通孔與該第三導電塊之該發光二極體之步驟中，更包含下列步驟：形成該第二導電塊於該第一面，以與該發光二極體電性連接；形成該導電通孔於該發光二極體中，以與該第二導電塊電性連接；形成該第三導電塊於該第二面，並與該導電通孔電性連接；以及於該第一面形成該第二接合塊。
  18. 如請求項17所述之具有積體電路與發光二極體之異質整合結構之製作方法，其中形成該第二、第三導電塊係以光微影、電鍍及蝕刻製程進行，形成該第二接合塊係以光微影製程進行。
  19. 如請求項9所述之具有積體電路與發光二極體之異質整合結構之製作方法，更包含一切割步驟，其係對該積體電路及發光二極體進行切割，以成為複數異質整合單元。
TW100119755A 2011-06-07 2011-06-07 具有積體電路與發光二極體之異質整合結構及其製作方法 TWI434405B (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
TW100119755A TWI434405B (zh) 2011-06-07 2011-06-07 具有積體電路與發光二極體之異質整合結構及其製作方法
CN2011101922135A CN102263097A (zh) 2011-06-07 2011-07-11 具有集成电路与发光二极管的异质整合结构及其制作方法
JP2011163255A JP2012256810A (ja) 2011-06-07 2011-07-26 集積回路と発光ダイオードを備えた異種集積構造及びその製造方法
KR1020110087639A KR101259308B1 (ko) 2011-06-07 2011-08-31 아이씨와 엘이디를 포함하는 헤테로구조물와 이를 제조하기 위한 방법
US13/224,607 US8536613B2 (en) 2011-06-07 2011-09-02 Heterostructure containing IC and LED and method for fabricating the same
US14/019,933 US8679891B2 (en) 2011-06-07 2013-09-06 Heterostructure containing IC and LED and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100119755A TWI434405B (zh) 2011-06-07 2011-06-07 具有積體電路與發光二極體之異質整合結構及其製作方法

Publications (2)

Publication Number Publication Date
TW201250997A TW201250997A (en) 2012-12-16
TWI434405B true TWI434405B (zh) 2014-04-11

Family

ID=45009670

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100119755A TWI434405B (zh) 2011-06-07 2011-06-07 具有積體電路與發光二極體之異質整合結構及其製作方法

Country Status (5)

Country Link
US (2) US8536613B2 (zh)
JP (1) JP2012256810A (zh)
KR (1) KR101259308B1 (zh)
CN (1) CN102263097A (zh)
TW (1) TWI434405B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2992466A1 (fr) * 2012-06-22 2013-12-27 Soitec Silicon On Insulator Procede de realisation de contact pour led et structure resultante
JP6479577B2 (ja) * 2015-05-29 2019-03-06 東芝メモリ株式会社 半導体装置
JP6656836B2 (ja) * 2015-07-24 2020-03-04 新光電気工業株式会社 実装構造体及びその製造方法
CN114759130B (zh) * 2022-06-15 2022-09-02 镭昱光电科技(苏州)有限公司 一种Micro-LED显示芯片及其制备方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111347A (ja) * 1981-12-24 1983-07-02 Matsushita Electric Ind Co Ltd 半導体装置
JPH06334217A (ja) * 1993-05-25 1994-12-02 Victor Co Of Japan Ltd Ｌｅｄアレイ装置
JPH07131076A (ja) * 1993-11-08 1995-05-19 Victor Co Of Japan Ltd Ｌｅｄアレイ装置
DE59608981D1 (de) * 1995-05-22 2002-05-02 Oce Printing Systems Gmbh Optischer Zeichengenerator für ein elektrografisches Druck- oder Kopiergerät
JP3530442B2 (ja) 1999-12-24 2004-05-24 三洋電機株式会社 面光源装置の色度調整方法
JP3652945B2 (ja) * 1999-12-28 2005-05-25 松下電器産業株式会社 光情報処理装置
JP4122743B2 (ja) * 2001-09-19 2008-07-23 松下電工株式会社 発光装置
US7897979B2 (en) * 2002-06-07 2011-03-01 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and manufacturing method thereof
US20030227020A1 (en) * 2002-06-10 2003-12-11 Excellence Optoelectronics Inc. Light emitting apparatus with current regulation function
US7456035B2 (en) 2003-07-29 2008-11-25 Lumination Llc Flip chip light emitting diode devices having thinned or removed substrates
US7754507B2 (en) * 2005-06-09 2010-07-13 Philips Lumileds Lighting Company, Llc Method of removing the growth substrate of a semiconductor light emitting device
WO2007002297A2 (en) * 2005-06-24 2007-01-04 Crafts Douglas E Temporary planar electrical contact device and method using vertically-compressible nanotube contact structures
KR100634307B1 (ko) * 2005-08-10 2006-10-16 서울옵토디바이스주식회사 발광 소자 및 이의 제조 방법
WO2007037190A1 (ja) * 2005-09-27 2007-04-05 Matsushita Electric Industrial Co., Ltd. 放熱配線基板とその製造方法と放熱配線基板を用いた電気機器
JP4718305B2 (ja) * 2005-11-09 2011-07-06 新光電気工業株式会社 配線基板の製造方法および半導体装置の製造方法
TW200723556A (en) * 2005-12-06 2007-06-16 Tyntek Corp LED-based light emitting device having integrated rectifier circuit in substrate and method of manufacturing the same
TWI295115B (en) * 2006-02-13 2008-03-21 Ind Tech Res Inst Encapsulation and methods thereof
US7586125B2 (en) * 2006-02-20 2009-09-08 Industrial Technology Research Institute Light emitting diode package structure and fabricating method thereof
CN101401206B (zh) * 2006-03-29 2011-04-13 京瓷株式会社 电路组件和无线通信设备、以及电路组件的制造方法
JP2008112030A (ja) * 2006-10-31 2008-05-15 Sumitomo Bakelite Co Ltd 接着剤付き光回路基板、光素子実装用部品及び光素子実装部品
CN102067298B (zh) * 2008-06-25 2015-10-14 松下电器产业株式会社 安装结构体、以及安装结构体的制造方法
DE102008030584A1 (de) * 2008-06-27 2009-12-31 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Bauelementes und optoelektronisches Bauelement
JP5126127B2 (ja) * 2009-03-17 2013-01-23 豊田合成株式会社 発光装置の製造方法
JP2010263050A (ja) * 2009-05-01 2010-11-18 Showa Denko Kk 発光ダイオード及びその製造方法、並びに発光ダイオードランプ
KR101105006B1 (ko) 2009-10-28 2012-01-16 이용현 엘이디방열어셈블리 및 엘이디방열어셈블리의 제조방법
US8492788B2 (en) * 2010-10-08 2013-07-23 Guardian Industries Corp. Insulating glass (IG) or vacuum insulating glass (VIG) unit including light source, and/or methods of making the same

Also Published As

Publication number Publication date
US20120313133A1 (en) 2012-12-13
US8679891B2 (en) 2014-03-25
JP2012256810A (ja) 2012-12-27
TW201250997A (en) 2012-12-16
CN102263097A (zh) 2011-11-30
US20140004630A1 (en) 2014-01-02
KR101259308B1 (ko) 2013-05-06
KR20120135853A (ko) 2012-12-17
US8536613B2 (en) 2013-09-17

Similar Documents

Publication Publication Date Title
JP5296894B2 (ja) パッケージキャリアおよびその製造方法
US20070096272A1 (en) Light emitting diode package
TWI381564B (zh) 發光二極體
JP2011071274A (ja) 半導体装置及びその製造方法
TW201131828A (en) LED flip-chip package structure with dummy bumps
TWI434405B (zh) 具有積體電路與發光二極體之異質整合結構及其製作方法
KR20150030259A (ko) 플립칩 적층을 위한 방법
TWI455366B (zh) 發光二極體封裝結構的製造方法
TW201426969A (zh) 高壓覆晶ｌｅｄ結構及其製造方法
TWI484674B (zh) 電子元件
TWI651874B (zh) 發光裝置及其製造方法
US8841172B2 (en) Method for forming package substrate
US20140191386A1 (en) Semiconductor package and fabrication method thereof
KR101132754B1 (ko) 엘이디 베어칩 제조방법
TWI557953B (zh) 發光二極體覆晶封裝結構及其製造方法
Liu et al. Low thermal-resistance silicon-based substrate for light-emitting diode packaging
TWI744194B (zh) 發光二極體封裝結構及其製作方法
JP6103401B2 (ja) 配線基板およびｌｅｄモジュール
TW201347616A (zh) 發光二極體封裝及所使用之ｐｃｂ式散熱基板與其製法
TWI330417B (zh)
TWI469314B (zh) 發光二極體的製造方法
TWM494264U (zh) 發光二極體封裝(LED package)及所使用之ＰＣＢ式散熱基板
Dong et al. Novel system-in-package design and packaging solution for solid state lighting systems
TW201501258A (zh) 覆晶晶片級封裝之複合式載板結構及其製法
TW201246613A (en) Optoelectronic semiconductor package structure with electrostatic discharge protection capability

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees