KR101087311B1 - 반도체 장치를 제조하는 방법 - Google Patents

반도체 장치를 제조하는 방법 Download PDF

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Publication number
KR101087311B1
KR101087311B1 KR1020090016754A KR20090016754A KR101087311B1 KR 101087311 B1 KR101087311 B1 KR 101087311B1 KR 1020090016754 A KR1020090016754 A KR 1020090016754A KR 20090016754 A KR20090016754 A KR 20090016754A KR 101087311 B1 KR101087311 B1 KR 101087311B1
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South Korea
Prior art keywords
core material
film
cover film
sidewall spacer
forming
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KR1020090016754A
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English (en)
Korean (ko)
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KR20090093869A (ko
Inventor
게이스께 기꾸따니
가쯔노리 야하시
Original Assignee
가부시끼가이샤 도시바
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
KR1020090016754A 2008-02-29 2009-02-27 반도체 장치를 제조하는 방법 Expired - Fee Related KR101087311B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2008-051240 2008-02-29
JP2008051240A JP4630906B2 (ja) 2008-02-29 2008-02-29 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR20090093869A KR20090093869A (ko) 2009-09-02
KR101087311B1 true KR101087311B1 (ko) 2011-11-25

Family

ID=41013514

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090016754A Expired - Fee Related KR101087311B1 (ko) 2008-02-29 2009-02-27 반도체 장치를 제조하는 방법

Country Status (3)

Country Link
US (1) US8088689B2 (enExample)
JP (1) JP4630906B2 (enExample)
KR (1) KR101087311B1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5160302B2 (ja) * 2008-05-19 2013-03-13 株式会社東芝 半導体装置の製造方法
JP5606388B2 (ja) * 2011-05-13 2014-10-15 株式会社東芝 パターン形成方法
JP2013197266A (ja) 2012-03-19 2013-09-30 Toshiba Corp 半導体装置およびその製造方法
US9564361B2 (en) * 2013-09-13 2017-02-07 Qualcomm Incorporated Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
US9847339B2 (en) * 2016-04-12 2017-12-19 Macronix International Co., Ltd. Self-aligned multiple patterning semiconductor device fabrication
JP6981945B2 (ja) 2018-09-13 2021-12-17 信越化学工業株式会社 パターン形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4838991A (en) 1987-10-30 1989-06-13 International Business Machines Corporation Process for defining organic sidewall structures
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435916A (en) * 1987-07-31 1989-02-07 Hitachi Ltd Formation of fine pattern
JPH01119028A (ja) * 1987-10-30 1989-05-11 Nec Corp 半導体装置の製造方法
US6924191B2 (en) * 2002-06-20 2005-08-02 Applied Materials, Inc. Method for fabricating a gate structure of a field effect transistor
JP2006032648A (ja) * 2004-07-16 2006-02-02 Toshiba Corp パターン形成方法を含む半導体装置の製造方法
US7253118B2 (en) * 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
JP4921723B2 (ja) * 2005-04-18 2012-04-25 株式会社東芝 半導体装置の製造方法
JP4271243B2 (ja) * 2006-04-11 2009-06-03 株式会社東芝 集積回路パターンの形成方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4838991A (en) 1987-10-30 1989-06-13 International Business Machines Corporation Process for defining organic sidewall structures
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process

Also Published As

Publication number Publication date
US20090221147A1 (en) 2009-09-03
JP2009212163A (ja) 2009-09-17
JP4630906B2 (ja) 2011-02-09
US8088689B2 (en) 2012-01-03
KR20090093869A (ko) 2009-09-02

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