KR101046862B1 - 낮은 k 이중 다마신 집적회로들의 형성에 사용할 수 있는 유기 barc 식각 프로세스 - Google Patents
낮은 k 이중 다마신 집적회로들의 형성에 사용할 수 있는 유기 barc 식각 프로세스 Download PDFInfo
- Publication number
- KR101046862B1 KR101046862B1 KR1020087025159A KR20087025159A KR101046862B1 KR 101046862 B1 KR101046862 B1 KR 101046862B1 KR 1020087025159 A KR1020087025159 A KR 1020087025159A KR 20087025159 A KR20087025159 A KR 20087025159A KR 101046862 B1 KR101046862 B1 KR 101046862B1
- Authority
- KR
- South Korea
- Prior art keywords
- etching
- planarization layer
- organic planarization
- plasma reactor
- organic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
- H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
- H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
- H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/385,256 US7828987B2 (en) | 2006-03-20 | 2006-03-20 | Organic BARC etch process capable of use in the formation of low K dual damascene integrated circuits |
| US11/385,256 | 2006-03-20 | ||
| PCT/US2007/007010 WO2007123616A2 (en) | 2006-03-20 | 2007-03-20 | Organic barc etch process capable of use in the formation of low k dual damascene integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20080109849A KR20080109849A (ko) | 2008-12-17 |
| KR101046862B1 true KR101046862B1 (ko) | 2011-07-06 |
Family
ID=38518439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020087025159A Expired - Fee Related KR101046862B1 (ko) | 2006-03-20 | 2007-03-20 | 낮은 k 이중 다마신 집적회로들의 형성에 사용할 수 있는 유기 barc 식각 프로세스 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7828987B2 (https=) |
| EP (1) | EP2002467A2 (https=) |
| JP (1) | JP2009530863A (https=) |
| KR (1) | KR101046862B1 (https=) |
| CN (1) | CN101449363B (https=) |
| WO (1) | WO2007123616A2 (https=) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9196270B1 (en) | 2006-12-07 | 2015-11-24 | Western Digital (Fremont), Llc | Method for providing a magnetoresistive element having small critical dimensions |
| DE102007010563A1 (de) * | 2007-02-22 | 2008-08-28 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Selektives Wachstum von polykristallinem siliziumhaltigen Halbleitermaterial auf siliziumhaltiger Halbleiteroberfläche |
| US8003488B2 (en) * | 2007-09-26 | 2011-08-23 | International Business Machines Corporation | Shallow trench isolation structure compatible with SOI embedded DRAM |
| SG187508A1 (en) * | 2008-02-01 | 2013-02-28 | Lam Res Corp | Reducing damage to low-k materials during photoresist stripping |
| DE102008016424B4 (de) * | 2008-03-31 | 2011-06-01 | Amd Fab 36 Limited Liability Company & Co. Kg | Verfahren mit einem Bilden einer Kontaktloshöffnung und eines Grabens in einer dielektrischen Schicht mit kleinem ε |
| US8316527B2 (en) | 2008-04-01 | 2012-11-27 | Western Digital (Fremont), Llc | Method for providing at least one magnetoresistive device |
| US20090286402A1 (en) * | 2008-05-13 | 2009-11-19 | Applied Materials, Inc | Method for critical dimension shrink using conformal pecvd films |
| US8349195B1 (en) | 2008-06-27 | 2013-01-08 | Western Digital (Fremont), Llc | Method and system for providing a magnetoresistive structure using undercut free mask |
| US8138093B2 (en) * | 2009-08-12 | 2012-03-20 | International Business Machines Corporation | Method for forming trenches having different widths and the same depth |
| US8513129B2 (en) * | 2010-05-28 | 2013-08-20 | Applied Materials, Inc. | Planarizing etch hardmask to increase pattern density and aspect ratio |
| CN103107158A (zh) * | 2011-11-11 | 2013-05-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| CN103165576B (zh) * | 2011-12-13 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其制造方法 |
| US8551877B2 (en) * | 2012-03-07 | 2013-10-08 | Tokyo Electron Limited | Sidewall and chamfer protection during hard mask removal for interconnect patterning |
| CN102891103B (zh) * | 2012-09-17 | 2015-01-21 | 上海华力微电子有限公司 | 一种制备顶层金属互联工艺刻蚀中间停止层的方法 |
| JP2014165191A (ja) * | 2013-02-21 | 2014-09-08 | Seiko Instruments Inc | 紫外線消去型の不揮発性半導体装置 |
| US9400529B2 (en) | 2013-09-27 | 2016-07-26 | Apple Inc. | Electronic device having housing with embedded interconnects |
| US20150118832A1 (en) * | 2013-10-24 | 2015-04-30 | Applied Materials, Inc. | Methods for patterning a hardmask layer for an ion implantation process |
| US9385086B2 (en) * | 2013-12-10 | 2016-07-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bi-layer hard mask for robust metallization profile |
| US9093387B1 (en) * | 2014-01-08 | 2015-07-28 | International Business Machines Corporation | Metallic mask patterning process for minimizing collateral etch of an underlayer |
| US9385000B2 (en) * | 2014-01-24 | 2016-07-05 | United Microelectronics Corp. | Method of performing etching process |
| US9454177B2 (en) | 2014-02-14 | 2016-09-27 | Apple Inc. | Electronic devices with housing-based interconnects and coupling structures |
| CN105097493B (zh) * | 2014-04-24 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | 一种制作半导体器件的方法 |
| CN104900510B (zh) * | 2015-06-29 | 2018-01-26 | 上海华力微电子有限公司 | 刻蚀映射关系模型和控制浅槽隔离刻蚀关键尺寸的方法 |
| US9859156B2 (en) * | 2015-12-30 | 2018-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure with sidewall dielectric protection layer |
| US10157773B1 (en) | 2017-11-28 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure having layer with re-entrant profile and method of forming the same |
| WO2020258124A1 (en) * | 2019-06-27 | 2020-12-30 | Yangtze Memory Technologies Co., Ltd. | Interconnect structure and method of forming the same |
| CN113053805B (zh) * | 2021-03-11 | 2022-06-10 | 长鑫存储技术有限公司 | 半导体结构的形成方法及半导体结构 |
| CN115547823B (zh) * | 2021-06-30 | 2025-12-12 | 中微半导体设备(上海)股份有限公司 | 一种半导体结构的形成方法及半导体结构 |
| US12100615B2 (en) * | 2021-12-23 | 2024-09-24 | Nanya Technology Corporation | Method of manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861347B2 (en) * | 2001-05-17 | 2005-03-01 | Samsung Electronics Co., Ltd. | Method for forming metal wiring layer of semiconductor device |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5338398A (en) * | 1991-03-28 | 1994-08-16 | Applied Materials, Inc. | Tungsten silicide etch process selective to photoresist and oxide |
| US5492597A (en) * | 1994-05-13 | 1996-02-20 | Micron Semiconductor, Inc. | Method of etching WSix films |
| EP0932190A1 (en) * | 1997-12-30 | 1999-07-28 | International Business Machines Corporation | Method of plasma etching the tungsten silicide layer in the gate conductor stack formation |
| US6211092B1 (en) * | 1998-07-09 | 2001-04-03 | Applied Materials, Inc. | Counterbore dielectric plasma etch process particularly useful for dual damascene |
| US6407004B1 (en) * | 1999-05-12 | 2002-06-18 | Matsushita Electric Industrial Co., Ltd. | Thin film device and method for manufacturing thin film device |
| US6451703B1 (en) * | 2000-03-10 | 2002-09-17 | Applied Materials, Inc. | Magnetically enhanced plasma etch process using a heavy fluorocarbon etching gas |
| JP3974319B2 (ja) * | 2000-03-30 | 2007-09-12 | 株式会社東芝 | エッチング方法 |
| TW479322B (en) * | 2000-09-25 | 2002-03-11 | United Microelectronics Corp | Manufacturing method of local inter connect contact opening |
| US6376366B1 (en) * | 2001-05-21 | 2002-04-23 | Taiwan Semiconductor Manufacturing Company | Partial hard mask open process for hard mask dual damascene etch |
| US6875699B1 (en) * | 2001-06-21 | 2005-04-05 | Lam Research Corporation | Method for patterning multilevel interconnects |
| US6495469B1 (en) * | 2001-12-03 | 2002-12-17 | Taiwan Semiconductor Manufacturing Company | High selectivity, low etch depth micro-loading process for non stop layer damascene etch |
| KR100464430B1 (ko) * | 2002-08-20 | 2005-01-03 | 삼성전자주식회사 | 하드 마스크를 이용한 알루미늄막 식각 방법 및 반도체소자의 배선 형성 방법 |
| US7109119B2 (en) * | 2002-10-31 | 2006-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scum solution for chemically amplified resist patterning in cu/low k dual damascene |
| US6774031B2 (en) * | 2002-12-17 | 2004-08-10 | Texas Instruments Incorporated | Method of forming dual-damascene structure |
| WO2004061919A1 (en) * | 2002-12-23 | 2004-07-22 | Tokyo Electron Limited | Method and apparatus for bilayer photoresist dry development |
| US6900123B2 (en) * | 2003-03-20 | 2005-05-31 | Texas Instruments Incorporated | BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control |
| JP2007537602A (ja) * | 2004-05-11 | 2007-12-20 | アプライド マテリアルズ インコーポレイテッド | フルオロカーボン化学エッチングにおけるh2添加物を使用しての炭素ドープ酸化ケイ素エッチング |
-
2006
- 2006-03-20 US US11/385,256 patent/US7828987B2/en not_active Expired - Fee Related
-
2007
- 2007-03-20 JP JP2009501539A patent/JP2009530863A/ja active Pending
- 2007-03-20 EP EP07753620A patent/EP2002467A2/en not_active Withdrawn
- 2007-03-20 KR KR1020087025159A patent/KR101046862B1/ko not_active Expired - Fee Related
- 2007-03-20 WO PCT/US2007/007010 patent/WO2007123616A2/en not_active Ceased
- 2007-03-20 CN CN2007800183975A patent/CN101449363B/zh not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861347B2 (en) * | 2001-05-17 | 2005-03-01 | Samsung Electronics Co., Ltd. | Method for forming metal wiring layer of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007123616A2 (en) | 2007-11-01 |
| US7828987B2 (en) | 2010-11-09 |
| KR20080109849A (ko) | 2008-12-17 |
| JP2009530863A (ja) | 2009-08-27 |
| WO2007123616A3 (en) | 2008-08-28 |
| CN101449363B (zh) | 2010-12-01 |
| CN101449363A (zh) | 2009-06-03 |
| EP2002467A2 (en) | 2008-12-17 |
| US20070218679A1 (en) | 2007-09-20 |
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