KR101006286B1 - 제조공정의 후 공정에서 서스펜드된 전송 라인 구조를형성하기 위한 방법 - Google Patents

제조공정의 후 공정에서 서스펜드된 전송 라인 구조를형성하기 위한 방법 Download PDF

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KR101006286B1
KR101006286B1 KR1020067020388A KR20067020388A KR101006286B1 KR 101006286 B1 KR101006286 B1 KR 101006286B1 KR 1020067020388 A KR1020067020388 A KR 1020067020388A KR 20067020388 A KR20067020388 A KR 20067020388A KR 101006286 B1 KR101006286 B1 KR 101006286B1
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Prior art keywords
transmission line
signal transmission
voids
sacrificial material
ground plane
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KR20070018899A (ko
Inventor
아닐 케이. 친타킨디
로버트 에이. 그로베스
요우리 브이. 트리티아코브
쿠날 바에드
리차드 피. 볼랜트
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인터내셔널 비지네스 머신즈 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P11/00—Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
    • H01P11/001—Manufacturing waveguides or transmission lines of the waveguide type
    • H01P11/003—Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/423—Shielding layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/209—Vertical interconnections, e.g. vias
    • H10W44/212—Coaxial feed-throughs in substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/216—Waveguides, e.g. strip lines

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020067020388A 2004-04-29 2005-04-28 제조공정의 후 공정에서 서스펜드된 전송 라인 구조를형성하기 위한 방법 Expired - Fee Related KR101006286B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/709,357 US7005371B2 (en) 2004-04-29 2004-04-29 Method of forming suspended transmission line structures in back end of line processing
US10/709,357 2004-04-29
PCT/US2005/014645 WO2005112105A1 (en) 2004-04-29 2005-04-28 Method for forming suspended transmission line structures in back end of line processing

Publications (2)

Publication Number Publication Date
KR20070018899A KR20070018899A (ko) 2007-02-14
KR101006286B1 true KR101006286B1 (ko) 2011-01-06

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KR1020067020388A Expired - Fee Related KR101006286B1 (ko) 2004-04-29 2005-04-28 제조공정의 후 공정에서 서스펜드된 전송 라인 구조를형성하기 위한 방법

Country Status (7)

Country Link
US (2) US7005371B2 (https=)
EP (1) EP1756862A4 (https=)
JP (1) JP4776618B2 (https=)
KR (1) KR101006286B1 (https=)
CN (1) CN100423216C (https=)
TW (1) TWI464840B (https=)
WO (1) WO2005112105A1 (https=)

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Publication number Publication date
WO2005112105A1 (en) 2005-11-24
US7608909B2 (en) 2009-10-27
EP1756862A4 (en) 2011-03-02
TWI464840B (zh) 2014-12-11
US20060197119A1 (en) 2006-09-07
CN1947234A (zh) 2007-04-11
US7005371B2 (en) 2006-02-28
EP1756862A1 (en) 2007-02-28
TW200603368A (en) 2006-01-16
JP4776618B2 (ja) 2011-09-21
CN100423216C (zh) 2008-10-01
KR20070018899A (ko) 2007-02-14
JP2007535825A (ja) 2007-12-06
US20050245063A1 (en) 2005-11-03

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