KR100866826B1 - CMOS 디바이스를 위한 변형된 Si를 형성하는 방법 및구조 - Google Patents
CMOS 디바이스를 위한 변형된 Si를 형성하는 방법 및구조 Download PDFInfo
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- KR100866826B1 KR100866826B1 KR1020067008867A KR20067008867A KR100866826B1 KR 100866826 B1 KR100866826 B1 KR 100866826B1 KR 1020067008867 A KR1020067008867 A KR 1020067008867A KR 20067008867 A KR20067008867 A KR 20067008867A KR 100866826 B1 KR100866826 B1 KR 100866826B1
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- semiconductor substrate
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- H01L21/02367—Substrates
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
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- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/605,906 US7129126B2 (en) | 2003-11-05 | 2003-11-05 | Method and structure for forming strained Si for CMOS devices |
| US10/605,906 | 2003-11-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20060108663A KR20060108663A (ko) | 2006-10-18 |
| KR100866826B1 true KR100866826B1 (ko) | 2008-11-04 |
Family
ID=34549690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020067008867A Expired - Fee Related KR100866826B1 (ko) | 2003-11-05 | 2004-11-05 | CMOS 디바이스를 위한 변형된 Si를 형성하는 방법 및구조 |
Country Status (6)
| Country | Link |
|---|---|
| US (5) | US7129126B2 (enExample) |
| EP (1) | EP1680804A4 (enExample) |
| JP (1) | JP4959337B2 (enExample) |
| KR (1) | KR100866826B1 (enExample) |
| CN (1) | CN100555600C (enExample) |
| WO (1) | WO2005045901A2 (enExample) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7037770B2 (en) * | 2003-10-20 | 2006-05-02 | International Business Machines Corporation | Method of manufacturing strained dislocation-free channels for CMOS |
| US7129126B2 (en) * | 2003-11-05 | 2006-10-31 | International Business Machines Corporation | Method and structure for forming strained Si for CMOS devices |
| US7029964B2 (en) * | 2003-11-13 | 2006-04-18 | International Business Machines Corporation | Method of manufacturing a strained silicon on a SiGe on SOI substrate |
| US20050287747A1 (en) * | 2004-06-29 | 2005-12-29 | International Business Machines Corporation | Doped nitride film, doped oxide film and other doped films |
| US7176481B2 (en) * | 2005-01-12 | 2007-02-13 | International Business Machines Corporation | In situ doped embedded sige extension and source/drain for enhanced PFET performance |
| US7078285B1 (en) * | 2005-01-21 | 2006-07-18 | Sony Corporation | SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material |
| US8972300B2 (en) * | 2006-04-27 | 2015-03-03 | Panasonic Corporation | Content distribution system |
| US7781839B2 (en) * | 2007-03-30 | 2010-08-24 | Freescale Semiconductor, Inc. | Structure and method for strained transistor directly on insulator |
| US7572689B2 (en) * | 2007-11-09 | 2009-08-11 | International Business Machines Corporation | Method and structure for reducing induced mechanical stresses |
| US7678634B2 (en) * | 2008-01-28 | 2010-03-16 | International Business Machines Corporation | Local stress engineering for CMOS devices |
| US8115194B2 (en) * | 2008-02-21 | 2012-02-14 | United Microelectronics Corp. | Semiconductor device capable of providing identical strains to each channel region of the transistors |
| FR2934416B1 (fr) * | 2008-07-24 | 2011-09-02 | Inst Nat Sciences Appliq | Substrat semi-conducteur contraint et procede de fabrication associe. |
| US8368125B2 (en) | 2009-07-20 | 2013-02-05 | International Business Machines Corporation | Multiple orientation nanowires with gate stack stressors |
| US20110031503A1 (en) * | 2009-08-10 | 2011-02-10 | International Business Machines Corporation | Device with stressed channel |
| US8138523B2 (en) | 2009-10-08 | 2012-03-20 | International Business Machines Corporation | Semiconductor device having silicon on stressed liner (SOL) |
| CN102315126A (zh) * | 2010-07-07 | 2012-01-11 | 中国科学院微电子研究所 | 半导体器件及其制作方法 |
| US20130137235A1 (en) * | 2010-07-15 | 2013-05-30 | University Of Electronic Science And Technology Of China | Mos transistor using stress concentration effect for enhancing stress in channel area |
| CN104425280B (zh) * | 2013-09-09 | 2018-08-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件结构及其形成方法 |
| US9368626B2 (en) * | 2013-12-04 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with strained layer |
| US9515181B2 (en) | 2014-08-06 | 2016-12-06 | Qualcomm Incorporated | Semiconductor device with self-aligned back side features |
| GB201415119D0 (en) * | 2014-08-27 | 2014-10-08 | Ibm | Method for fabricating a semiconductor structure |
| US10079233B2 (en) * | 2016-09-28 | 2018-09-18 | International Business Machines Corporation | Semiconductor device and method of forming the semiconductor device |
| DE102019122987A1 (de) | 2019-08-27 | 2021-03-04 | Zf Airbag Germany Gmbh | Diffusor für einen Gasgenerator, Gasgenerator mit einem solchen Diffusor und Herstellungsverfahren für einen solchen Diffusor |
| US11502106B2 (en) * | 2020-02-11 | 2022-11-15 | Globalfoundries U.S. Inc. | Multi-layered substrates of semiconductor devices |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010003364A1 (en) * | 1998-05-27 | 2001-06-14 | Sony Corporation | Semiconductor and fabrication method thereof |
| US20020086472A1 (en) * | 2000-12-29 | 2002-07-04 | Brian Roberds | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel |
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| US3602841A (en) * | 1970-06-18 | 1971-08-31 | Ibm | High frequency bulk semiconductor amplifiers and oscillators |
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| JPS61198743A (ja) * | 1985-02-28 | 1986-09-03 | New Japan Radio Co Ltd | 半導体装置の製造方法 |
| US4665415A (en) * | 1985-04-24 | 1987-05-12 | International Business Machines Corporation | Semiconductor device with hole conduction via strained lattice |
| EP0219641B1 (de) * | 1985-09-13 | 1991-01-09 | Siemens Aktiengesellschaft | Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung |
| JPS6476755A (en) | 1987-09-18 | 1989-03-22 | Hitachi Ltd | Semiconductor device |
| US4958213A (en) * | 1987-12-07 | 1990-09-18 | Texas Instruments Incorporated | Method for forming a transistor base region under thick oxide |
| NL8800847A (nl) * | 1988-04-05 | 1989-11-01 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een soi-struktuur. |
| US5354695A (en) * | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
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| US5006913A (en) * | 1988-11-05 | 1991-04-09 | Mitsubishi Denki Kabushiki Kaisha | Stacked type semiconductor device |
| US5108843A (en) * | 1988-11-30 | 1992-04-28 | Ricoh Company, Ltd. | Thin film semiconductor and process for producing the same |
| US5241197A (en) * | 1989-01-25 | 1993-08-31 | Hitachi, Ltd. | Transistor provided with strained germanium layer |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2005045901A8 (en) | 2006-02-02 |
| US20100109048A1 (en) | 2010-05-06 |
| WO2005045901A2 (en) | 2005-05-19 |
| CN101164157A (zh) | 2008-04-16 |
| US7429752B2 (en) | 2008-09-30 |
| US7129126B2 (en) | 2006-10-31 |
| JP2007511078A (ja) | 2007-04-26 |
| US7700951B2 (en) | 2010-04-20 |
| KR20060108663A (ko) | 2006-10-18 |
| US20050093076A1 (en) | 2005-05-05 |
| EP1680804A2 (en) | 2006-07-19 |
| US7928443B2 (en) | 2011-04-19 |
| US20080003735A1 (en) | 2008-01-03 |
| US20080283824A1 (en) | 2008-11-20 |
| JP4959337B2 (ja) | 2012-06-20 |
| US7550338B2 (en) | 2009-06-23 |
| CN100555600C (zh) | 2009-10-28 |
| US20070020806A1 (en) | 2007-01-25 |
| EP1680804A4 (en) | 2008-07-09 |
| WO2005045901A3 (en) | 2006-08-17 |
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