JP4959337B2 - CMOSデバイスのための歪みSiを形成する方法及び構造体 - Google Patents

CMOSデバイスのための歪みSiを形成する方法及び構造体 Download PDF

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JP4959337B2
JP4959337B2 JP2006538524A JP2006538524A JP4959337B2 JP 4959337 B2 JP4959337 B2 JP 4959337B2 JP 2006538524 A JP2006538524 A JP 2006538524A JP 2006538524 A JP2006538524 A JP 2006538524A JP 4959337 B2 JP4959337 B2 JP 4959337B2
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semiconductor substrate
gap
layer
channel
strained layer
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JP2007511078A5 (enExample
JP2007511078A (ja
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スティーゲン、アン、エル
ヤン、ヘイニング、エス
チャン、イン
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International Business Machines Corp
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JP2006538524A 2003-11-05 2004-11-05 CMOSデバイスのための歪みSiを形成する方法及び構造体 Expired - Fee Related JP4959337B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/605,906 US7129126B2 (en) 2003-11-05 2003-11-05 Method and structure for forming strained Si for CMOS devices
US10/605,906 2003-11-05
PCT/US2004/037049 WO2005045901A2 (en) 2003-11-05 2004-11-05 METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES

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JP2007511078A JP2007511078A (ja) 2007-04-26
JP2007511078A5 JP2007511078A5 (enExample) 2007-11-15
JP4959337B2 true JP4959337B2 (ja) 2012-06-20

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US (5) US7129126B2 (enExample)
EP (1) EP1680804A4 (enExample)
JP (1) JP4959337B2 (enExample)
KR (1) KR100866826B1 (enExample)
CN (1) CN100555600C (enExample)
WO (1) WO2005045901A2 (enExample)

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US7429752B2 (en) 2008-09-30
US7129126B2 (en) 2006-10-31
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US7700951B2 (en) 2010-04-20
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US20050093076A1 (en) 2005-05-05
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US7928443B2 (en) 2011-04-19
US20080003735A1 (en) 2008-01-03
US20080283824A1 (en) 2008-11-20
US7550338B2 (en) 2009-06-23
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