KR100818720B1 - 반도체 메모리 장치의 레이턴시 제어 회로, 제어 방법 및상기 레이턴시 제어 회로를 포함하는 반도체 메모리 장치 - Google Patents

반도체 메모리 장치의 레이턴시 제어 회로, 제어 방법 및상기 레이턴시 제어 회로를 포함하는 반도체 메모리 장치 Download PDF

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Publication number
KR100818720B1
KR100818720B1 KR1020060063463A KR20060063463A KR100818720B1 KR 100818720 B1 KR100818720 B1 KR 100818720B1 KR 1020060063463 A KR1020060063463 A KR 1020060063463A KR 20060063463 A KR20060063463 A KR 20060063463A KR 100818720 B1 KR100818720 B1 KR 100818720B1
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KR
South Korea
Prior art keywords
signal
master
signals
latency
write
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KR1020060063463A
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English (en)
Korean (ko)
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KR20070053088A (ko
Inventor
김정열
김경호
방삼영
장성진
Original Assignee
삼성전자주식회사
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Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to US11/594,807 priority Critical patent/US7609584B2/en
Priority to TW095142111A priority patent/TW200739583A/zh
Priority to DE102006054998.8A priority patent/DE102006054998B4/de
Priority to JP2006313532A priority patent/JP5160770B2/ja
Priority to CN2006100644856A priority patent/CN101026006B/zh
Publication of KR20070053088A publication Critical patent/KR20070053088A/ko
Application granted granted Critical
Publication of KR100818720B1 publication Critical patent/KR100818720B1/ko
Priority to US12/585,428 priority patent/US7911862B2/en
Priority to JP2012061805A priority patent/JP2012113819A/ja

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
KR1020060063463A 2005-11-19 2006-07-06 반도체 메모리 장치의 레이턴시 제어 회로, 제어 방법 및상기 레이턴시 제어 회로를 포함하는 반도체 메모리 장치 KR100818720B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US11/594,807 US7609584B2 (en) 2005-11-19 2006-11-09 Latency control circuit and method thereof and an auto-precharge control circuit and method thereof
TW095142111A TW200739583A (en) 2005-11-19 2006-11-14 A latency control circuit, and method thereof and an auto-precharge control circuit and method thereof
DE102006054998.8A DE102006054998B4 (de) 2005-11-19 2006-11-17 Latenzsteuerschaltung, Halbleiterspeicherbauelement und Verfahren zum Steuern der Latenz
JP2006313532A JP5160770B2 (ja) 2005-11-19 2006-11-20 レイテンシー制御回路及びその方法、そして、自動プリチャージ制御回路及びその方法
CN2006100644856A CN101026006B (zh) 2005-11-19 2006-11-20 等待时间控制电路及其方法和包括其的半导体存储器设备
US12/585,428 US7911862B2 (en) 2005-11-19 2009-09-15 Latency control circuit and method thereof and an auto-precharge control circuit and method thereof
JP2012061805A JP2012113819A (ja) 2005-11-19 2012-03-19 自動プリチャージ制御回路と半導体メモリ装置とプリチャージング動作制御方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020050111027 2005-11-19
KR20050111027 2005-11-19

Publications (2)

Publication Number Publication Date
KR20070053088A KR20070053088A (ko) 2007-05-23
KR100818720B1 true KR100818720B1 (ko) 2008-04-01

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KR1020060063463A KR100818720B1 (ko) 2005-11-19 2006-07-06 반도체 메모리 장치의 레이턴시 제어 회로, 제어 방법 및상기 레이턴시 제어 회로를 포함하는 반도체 메모리 장치

Country Status (2)

Country Link
KR (1) KR100818720B1 (zh)
CN (1) CN101026006B (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100807236B1 (ko) * 2006-03-08 2008-02-28 삼성전자주식회사 입력 레이턴시 제어회로를 포함하는 반도체 메모리 장치 및입력 레이턴시 제어방법
US8984320B2 (en) * 2011-03-29 2015-03-17 Micron Technology, Inc. Command paths, apparatuses and methods for providing a command to a data block
KR101898176B1 (ko) * 2012-05-25 2018-09-12 에스케이하이닉스 주식회사 반도체 메모리 장치의 버퍼 제어회로
CN104391801B (zh) * 2014-11-07 2018-09-25 北京海尔集成电路设计有限公司 Ddrii控制器的读写、状态转换、物理地址分配方法
KR20180085419A (ko) * 2017-01-18 2018-07-27 삼성전자주식회사 불휘발성 메모리 장치, 불휘발성 메모리 장치의 동작 방법 및 불휘발성 메모리 장치를 포함하는 스토리지 장치
CN108632959B (zh) * 2017-03-24 2020-10-16 华为技术有限公司 一种站点唤醒方法及目标站点
US10153030B2 (en) * 2017-05-09 2018-12-11 Micron Technology, Inc. Apparatuses and methods for configurable command and data input circuits for semiconductor memories
US10170174B1 (en) * 2017-10-27 2019-01-01 Micron Technology, Inc. Apparatus and methods for refreshing memory
KR102412609B1 (ko) * 2017-11-03 2022-06-23 삼성전자주식회사 내부 커맨드에 따른 어드레스에 대한 저장 및 출력 제어를 수행하는 메모리 장치 및 그 동작방법
KR101989861B1 (ko) * 2018-07-30 2019-06-17 에스케이하이닉스 주식회사 반도체 메모리 장치의 버퍼 제어회로
US10878862B2 (en) * 2018-09-17 2020-12-29 Micron Technology, Inc. Apparatuses and methods for DRAM wordline control with reverse temperature coefficient delay
US11398815B2 (en) 2018-10-17 2022-07-26 Micron Technology, Inc. Methods and apparatuses for temperature independent delay circuitry
KR20210026965A (ko) * 2019-09-02 2021-03-10 삼성전자주식회사 클럭 트리를 포함하는 이미지 센서 및 어드레스 디코더, 이미지 센서를 포함하는 이미지 처리 시스템

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000032273A (ko) * 1998-11-13 2000-06-05 김영환 카스(cas)레이턴시(latency) 제어 회로
KR20020031853A (ko) * 2000-10-24 2002-05-03 윤종용 Ｊｅｄｅｃ 규격의 포스티드 카스 기능을 가지는 동기식반도체 메모리 장치
KR20040005517A (ko) * 2002-07-10 2004-01-16 삼성전자주식회사 고주파수 동작을 위한 동기식 반도체 장치의 레이턴시제어 회로 및 그 방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10047925A1 (de) * 2000-09-27 2002-05-02 Siemens Ag Verfahren zur Echtzeitkommunikation zwischen mehreren Netzwerkteilnehmern in einem Kommunikationssystem mit Ethernet-Physik sowie korrespondierendes Kommunikationssystem mit Ethernet-Physik
KR100543203B1 (ko) * 2003-03-20 2006-01-20 주식회사 하이닉스반도체 유효 데이타 윈도우의 조절이 가능한 반도체 메모리장치의 데이타 출력 버퍼

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000032273A (ko) * 1998-11-13 2000-06-05 김영환 카스(cas)레이턴시(latency) 제어 회로
KR20020031853A (ko) * 2000-10-24 2002-05-03 윤종용 Ｊｅｄｅｃ 규격의 포스티드 카스 기능을 가지는 동기식반도체 메모리 장치
KR20040005517A (ko) * 2002-07-10 2004-01-16 삼성전자주식회사 고주파수 동작을 위한 동기식 반도체 장치의 레이턴시제어 회로 및 그 방법

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Publication number Publication date
CN101026006B (zh) 2012-06-13
KR20070053088A (ko) 2007-05-23
CN101026006A (zh) 2007-08-29

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