KR100763961B1 - TBGA semiconductor package and the fabrication method of the same - Google Patents

Abstract

A TV package and a method of manufacturing the same are disclosed. The present invention provides a display device comprising: at least one frame; and a circuit tape comprising a film, a circuit pattern layer patterned on the film, and a photosolder register formed on a portion other than the circuit pattern layer; A solder material penetrating through the circuit tape and filled in a via hole having a conductive layer on the inner wall thereof, a solder ball bonded to the solder material, and a semiconductor chip mounted in a cavity formed on a frame and energizing the solder ball; A semiconductor package and a method of manufacturing the same.

TV, Via Hole, Via Plugging, Flip Chip

Description

TBGA semiconductor package and the fabrication method of the same

1 is a cross-sectional view schematically showing a conventional TVA semiconductor package;

2 is a schematic cross-sectional view of a TVV semiconductor package according to an embodiment of the present disclosure;

3A to 3H illustrate a state after manufacturing the semiconductor package of FIG. 2 step by step.

Figure 3a is a cross-sectional view showing a state after the copper foil is attached on the film,

3B is a cross-sectional view illustrating a state after forming a via hole in the film of FIG. 3A;

3C is a cross-sectional view illustrating a state after forming a conductive layer in the via hole of FIG. 3B;

3D is a cross-sectional view showing a state after applying, exposing, developing, and back coating a photoresist to the film of FIG. 3C;

3E is a cross-sectional view showing a state after etching and peeling off the film of FIG. 3D;

3F is a cross-sectional view illustrating a state after applying a photosolder register to the film of FIG. 3E;

Figure 3g is a cross-sectional view showing a state after forming a multi-plated layer on the film of Figure 3f,                 

3H is a cross-sectional view illustrating a state after the frame is attached to the film of FIG. 3G and the solder material is filled in the via hole;

4 is a flowchart sequentially illustrating a process of manufacturing the semiconductor package of FIG. 2.

<Brief description of the main parts of the drawing>

10,20 ... semiconductor package 11,21 ... circuit tape

12,300 ... adhesive 13,23,310 ... frame

14,24 ... semiconductor chip 15 ... wire

16 Molding material 17, 27 Solder ball

21a, 31 ... polymer film 21b, 37 ... circuit pattern layer

21c, 38 Optical Solder Register 32 Metal Foil

33,200 ... Viahall 34,230 ... Conductor Floor

35 Solder register 36 Back coating material

39,210,320 ... plated layer 220 ... solder material

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TVA semiconductor package, and more particularly, to a TVI semiconductor package and a method of manufacturing the same, in which a separate conductive layer is formed to improve a filling rate of a solder material in a via hole when a circuit tape and a frame are combined. will be.

Typically, a tape ball grid array (TBGA) semiconductor package is a one-piece type in which a circuit tape on which a circuit pattern layer is formed is directly attached onto a heat sink for dissipating heat. It can be classified into a two-piece type attached to a plurality of frames of stiffeners and heat sinks.

In this TV package, a semiconductor chip is mounted through a cavity formed in a frame, a circuit pattern layer of the semiconductor chip and a circuit tape are electrically connected by wires, and solder balls are connected to a solder ball land part connected to the circuit pattern layer. It is a structure to be attached.

1 illustrates a conventional one-piece TVA semiconductor package 10.

Referring to the drawings, the semiconductor package 10 includes a circuit tape 11 having a circuit pattern layer formed thereon, a frame 13 attached to a lower surface of the circuit tape 11 via an adhesive member 12, and The semiconductor chip 14 mounted in the cavity 13a formed in the frame 13, the wire 15 for wire bonding the circuit tape 11 and the semiconductor chip 14, and a portion for molding the wire bonded portion are molded. A molding material 16 and a solder ball 17 attached to the circuit tape 11 is included.

The semiconductor package 10 having such a structure forms a via hole in the circuit tape 11 to compensate for electrical performance, and fills and melts a conductive material such as solder paste or solder balls in the via hole. It is then attached to some solder balls 17 to perform the grounding role. The filling process of the solder material in the via hole is called a via pulgging process. The via plugging process may be performed by screen printing or solder ball injection.

By the way, the conventional TV package 10 has the following problems.

The circuit tape 11 attaches a copper foil on a thin polymer film such as polyimide and forms a plurality of via holes. The solder hole is filled in the via hole to be melted at a predetermined temperature. In the via plugging process, the solder material filled in the via plugging process hardly adheres at the interface with the sidewalls of the via hole, thereby generating a large number of voids. This is because the sidewall of the via hole is made of a non-metallic polymer film. As a result of this, there is a problem in the reliability of the electrical connection with the solder ball later, and the electrical characteristics are also degraded.

The present invention is to solve the above problems, by forming a conductive material on the inner wall of the via hole to increase the adhesion to the solder material filled in the via hole, to improve the reliability of the electrical connection with the solder ball attached thereto It is an object of the present invention to provide a GE semiconductor package and a method of manufacturing the same.

In order to achieve the above object, the TV package semiconductor package according to an aspect of the present invention,

At least one frame;                     

A circuit tape attached to the frame, the circuit tape comprising a polymer film, a circuit pattern layer made of a metal material patterned on the film, and a photosolder register formed on a portion other than the circuit pattern layer;

A solder material penetrating the circuit tape and filled in a via hole in which an electrically conductive layer is formed on an inner wall;

A solder ball bonded to the solder material; And

And a semiconductor chip mounted on the cavity formed on the frame and energized with the solder balls.

According to another aspect of the present invention, a method of manufacturing a TVei semiconductor package is provided.

A first step of laminating the polymer film and the metal foil;

A second step of forming a plurality of via holes through the film to which the foil is attached;

A third step of forming a conductive conductive layer on the inner wall of the via hole;

A fourth step of patterning the metal foil to form a circuit pattern layer;

A fifth step of attaching the frame to the lower surface of the film through an adhesive; And

And a sixth step of filling a solder material in the via hole.

In addition, the conductive layer is formed by any one method selected from electroless plating and sputtering.

Moreover, in the fourth step,                     

Applying a photoresist to the top surface of the foil;

Exposing and developing the photoresist;

Front coating the anti-etching material on the entire surface of the opposing film to which the photoresist is applied; And

Etching the foil to form a circuit pattern layer, and removing the remaining photoresist and the material for preventing etching.

Hereinafter, a TVA semiconductor package and a method of manufacturing the same according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a TVA semiconductor package 20 according to an embodiment of the present invention.

Referring to the drawings, the semiconductor package 20 may include a circuit tape 21, a frame 23 attached to a lower surface of the circuit tape 21, for example, a heat spreader, and a frame 23. The semiconductor chip 24 mounted in the cavity 23a is included.

The circuit tape 21 is a polymer film 21a such as polyimide, a circuit pattern layer 21b made of metal foil, for example, copper, which is attached and patterned on the film 21a, and the circuit pattern layer ( 21b) includes a photo solder resistor (PSR) 21c formed at a portion where no portion is formed.

The semiconductor chip 24 is wire bonded by the circuit pattern layer 21b and the first wire 25a. The semiconductor chip 24 is molded with a molding material (not shown) including the wire bonded portion.                     

In addition, a via hole 200 is formed in the circuit tape 21, and a plating layer 210 made of a noble metal is plated on the bottom surface of the via hole 200. The via hole 200 is filled with a solder material 220, and the solder material 220 is bonded to a solder ball 27 having a grounding function. In this case, a conductive layer 230 having conductivity is formed on the sidewall of the via hole 200.

The conductive layer 230 is formed of a metal material having excellent conductivity, such as copper, and the thickness thereof is preferably about 0.1 to 5 micrometers. The conductive layer 230 having such a thickness enables the solder material 220 to be filled in the via plugging process to be melted and firmly contacted at the interface at the time of solidification. The conductive layer 230 can be formed by an electroless plating method or a sputtering method.

The manufacturing method of the TVA semiconductor package having such a structure will be described sequentially.

3A to 3H illustrate a state after fabrication of a TVA semiconductor package in stages according to an example of the present invention, and FIG. 4 is a flowchart sequentially illustrating these stages.

First, a film 31 made of a polymer resin such as polyimide and a metal foil, for example, a copper foil 32 are prepared, respectively, and then the copper foil 32 is laminated on the upper surface of the polymer film 31. (FIG. 3A, S10)

When the copper foil 32 is attached on the film 31, a plurality of via holes 33 are formed by punching or the like. At this time, although not shown in the drawing, it is preferable that sprocket holes are also formed at both edges on the film 31 supplied in the reel type. (FIGS. 3B and S20).

Subsequently, a conductive layer 34 made of a conductive material is formed on the inner wall of the via hole 33. The conductive layer 34 is, for example, a layer of copper, having a thickness of about 0.1 to 5 micrometers. It can be said that the conductive layer 34 having the thickness of such a thin film can be formed by an electroless plating method or a sputtering method (FIG. 3C, S30).

When the conductive layer 34 is formed in the via hole 33, the photoresist 35 is coated on the upper surface of the copper foil 32, and exposed and developed to form a pattern. In addition, the lower surface of the film 31 corresponding to the position opposite to the copper foil 32 is coated with the front coating material 36 to prevent the pitting phenomenon of other parts during the etching later (Fig. 3d, S40)

Next, an etching process is performed using a predetermined etching solution to form a circuit pattern layer 37 on the upper surface of the film 31, and then remove the remaining photoresist 35 or back coating material 36. Done. As a result, a circuit pattern layer 37 having a predetermined design rule is completed on the upper surface of the film 31. (FIG. 3E, S50).

After the circuit pattern layer 37 is completed, the photosolder register 38 is formed in a region in which the circuit pattern layer 37 is not formed in the foil 32. In other words, the photosolder resist raw material is printed on the film 31, exposed, developed and dried to form the photosolder register 38 in a portion other than the circuit pattern layer 37. (FIG. 3F, S60). )                     

Subsequently, a multiplated layer 39 is formed on the upper surface of the circuit pattern layer 37 to prevent wire bonding and to prevent oxidation. For example, the nickel plating layer 39a is formed on the upper surface of the circuit pattern layer 37 as a base plating layer, and then a gold plating layer 39b, which is a noble metal, is sequentially formed on the upper surface of the circuit pattern layer 37 (FIG. 3G, S70).

Next, the frame 310 is attached to the lower surface of the film 31 through the adhesive 300. In this case, it will be advantageous to form the silver plating layer 320 in the region corresponding to the via hole 33 on the upper surface of the frame 310 in order to improve the adhesion with the solder material later (S80). )

The via hole 33 formed in the film 31 attached to the frame 310 is filled with the solder material 330 through a via plugging process. That is, the screen mask having a pattern corresponding to the via hole 33 separately provided is brought into close contact on the film 31 on which the circuit pattern layer 37 is formed, and then the solder material is a paste mixed with solder balls and flux. 330 is pushed in one direction using a squeegee to fill it in the via hole 33 (FIG. 3H, S90).

In the subsequent process, the solder material 330 is melted and solidified, and then the semiconductor chip is mounted in a cavity of the frame 310 formed by another process, and then molded using a wire bonding and molding material to form one TV. The semiconductor package is completed.

As described above, the TVA semiconductor package and a method of manufacturing the same of the present invention can obtain the following effects.                     

First, as the conductive layer is formed on the inner wall of the via hole, adhesion to the solder material filled during the via plugging process is improved.

Second, voids are generated at the interface between the via hole and the solder ball, thereby minimizing electrical performance and ensuring the reliability of the semiconductor package.

Third, instead of a semiconductor package using a two-piece frame, a film having a double layer copper pattern layer formed with via holes can be substituted, and manufacturing cost is reduced.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various changes and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (4)

At least one frame; A circuit tape attached to the frame, the circuit tape comprising a polymer film, a circuit pattern layer made of a metal material patterned on the polymer film, and an optical solder register formed at a portion other than the circuit pattern layer; A conductive layer formed on an inner wall of the via hole formed through the circuit tape; A solder material filled in the via hole and in contact with the conductive layer; A solder ball bonded to the solder material; And And a semiconductor chip mounted on the cavity formed on the frame and connected to the circuit pattern layer by a wire and energized with solder balls. A first step of laminating the polymer film and the metal foil; A second step of forming a plurality of via holes through the polymer film to which the metal foil is attached; Forming a conductive layer having conductivity on an inner sidewall of the via hole; A fourth step of patterning the metal foil to form a circuit pattern layer; A fifth step of forming a photosolder resistor layer in a region in which the circuit pattern layer is not formed in the metal foil; Attaching a frame to the lower surface of the polymer film through an adhesive; And And a seventh step of filling a solder material into the via hole. The method of claim 2, In the third stage, The conductive layer is formed by any method selected from the electroless plating method and the sputtering method. The method of claim 2, In the fourth step, Applying a photoresist to an upper surface of the metal foil; Exposing and developing the photoresist; Front coating the anti-etching material on the entire surface of the opposite polymer film to which the photoresist is applied; And Etching the metal foil to form a circuit pattern layer, and removing remaining photoresist and material for preventing etching.

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