KR950034445A - Etching Method of Lead Frame for Semiconductor Chip - Google Patents

Etching Method of Lead Frame for Semiconductor Chip Download PDF

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Publication number
KR950034445A
KR950034445A KR1019940011028A KR19940011028A KR950034445A KR 950034445 A KR950034445 A KR 950034445A KR 1019940011028 A KR1019940011028 A KR 1019940011028A KR 19940011028 A KR19940011028 A KR 19940011028A KR 950034445 A KR950034445 A KR 950034445A
Authority
KR
South Korea
Prior art keywords
photoresist
workpiece
etching
iii
lead frame
Prior art date
Application number
KR1019940011028A
Other languages
Korean (ko)
Inventor
오창연
윤현수
Original Assignee
이대원
삼성항공산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 이대원, 삼성항공산업 주식회사 filed Critical 이대원
Priority to KR1019940011028A priority Critical patent/KR950034445A/en
Publication of KR950034445A publication Critical patent/KR950034445A/en

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  • Lead Frames For Integrated Circuits (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

본 발명의 반도체칩용 리드 프레임의 에칭 방법에 관한 것이다.The etching method of the lead frame for semiconductor chips of this invention is related.

본 발명은 가공소재의 표면을 세정시키기 위한 전처리 단계; 가공소재의 표면에 포토 레지스터를 도포하는 도포 단계; 도포된 포토레지스터의 감광성을 이용하여 포토 레지스터 막을 소정의 패턴에 따라 강광시키는 노광 단계; 포토 레지스터막에서 비노광된 부분은 세척하고, 노광된 부분은 경화시켜주는 현상 단계; 상기 도포-노광-현상 단계를 복수회 반복 실시하는 단계; 가공소재를 원하는 형상대로 가공하기 위해 에칭을 행하는 에칭 단계; 및 가공소재 표면의 포토 레지스터 잔여분을 제거하는 박리 단계를 포함하여 된 점에 특징이 있다.The present invention comprises a pretreatment step for cleaning the surface of the workpiece; An application step of applying a photoresist to the surface of the workpiece; An exposure step of lightening the photoresist film according to a predetermined pattern by using the photosensitivity of the applied photoresist; Developing the unexposed portions of the photoresist film and curing the exposed portions; Repeating the application-exposure-development step a plurality of times; An etching step of etching to process the workpiece into a desired shape; And a peeling step of removing the photoresist residue on the surface of the workpiece.

따라서, 2가지 이상의 합금으로 된 소재에 있어서도 각부위의 식각특성에 따라 도포층의 두께가 조정되므로, 에칭 시각부위의 도포층+가공소재의 에칭에 소요되는 시간을 거의 균등하게 할 수 있어 각리드의 폭이 균등한 소망하는 형태의 리드 프레임을 얻을 수 있다.Therefore, even in a material made of two or more alloys, the thickness of the coating layer is adjusted according to the etching characteristics of each portion, so that the time required for etching the coating layer + processing material at the etching time portion can be made almost even. It is possible to obtain a lead frame having a desired shape with a uniform width.

Description

반도체칩용 리드 프레임의 에칭방법Etching Method of Lead Frame for Semiconductor Chip

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제18도는 2가지 이상의 합금으로 된 가공소재를 나타낸 것으로서 각 합금의 구성비의 일예를 보인 단면도.Figure 18 is a cross-sectional view showing an example of the composition of each alloy, showing a workpiece made of two or more alloys.

Claims (3)

(i)가공소재의 표면을 세정시키기 위한 전처리 단계; (ⅱ)가공소재의 표면에 포토 레지스터를 도포하는 도포 단계; (ⅲ)도포된 포토 레지스터의 감광성을 이용하여 포토 레지스터막을 소정의 패턴에 따라 강광시키는 노광 단계; (ⅳ)포토 레지스터막에서 비노광된 부분은 세척하고, 노광된 부분은 경화시켜주는 현상 단계;(ⅴ) 상기 (ⅱ)~(ⅲ)~(ⅳ)단계를 복수회 반복 실시하는 단계; (ⅵ)가공소재를 원하는 형상대로 가공하기 위해 에칭을 행하는 단계; 및 (ⅶ)가공소재 표면의 포토 레지스터 잔여분을 게거하는 박리 단계를 포함하여 된것을 특징으로 하는 반도체칩용 리드 프레임의 에칭방법.(i) a pretreatment step for cleaning the surface of the workpiece; (Ii) an application step of applying a photoresist to the surface of the workpiece; (Iii) an exposure step of lowering the photoresist film in accordance with a predetermined pattern by using the photosensitivity of the applied photoresist; (Iii) developing the unexposed portion of the photoresist film and curing the exposed portion; (iii) repeatedly performing steps (ii) to (iii) to (iii) a plurality of times; (Iii) etching to process the workpiece into a desired shape; And (iii) a peeling step of removing the remaining photoresist on the surface of the workpiece. 제1항에 있어서, 상기 전처리 단계 후 최초로 도포되는 포토레지스터는 수용성인 것을 특징으로 하는 반도체칩용 리드 프레임의 에칭방법.2. The method of claim 1, wherein the first photoresist applied after the pretreatment step is water soluble. 제1항에 있어서, 상기 최초인 현상 단계 이후, 복수회 반복 실시되는 도포-노광-현상 단계에 사용되는 포토 레지스터는 지용성인 것을 특징으로 하는 반도체칩용 리드 프레임의 에칭방법.The method of etching a lead frame for a semiconductor chip according to claim 1, wherein the photoresist used in the application-exposure-development step which is repeatedly performed a plurality of times after the initial development step is fat-soluble. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940011028A 1994-05-20 1994-05-20 Etching Method of Lead Frame for Semiconductor Chip KR950034445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940011028A KR950034445A (en) 1994-05-20 1994-05-20 Etching Method of Lead Frame for Semiconductor Chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940011028A KR950034445A (en) 1994-05-20 1994-05-20 Etching Method of Lead Frame for Semiconductor Chip

Publications (1)

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KR950034445A true KR950034445A (en) 1995-12-28

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100530755B1 (en) * 1997-11-11 2006-02-28 삼성테크윈 주식회사 The method of making lead frame
KR100763961B1 (en) * 2001-05-14 2007-10-05 삼성테크윈 주식회사 TBGA semiconductor package and the fabrication method of the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100530755B1 (en) * 1997-11-11 2006-02-28 삼성테크윈 주식회사 The method of making lead frame
KR100763961B1 (en) * 2001-05-14 2007-10-05 삼성테크윈 주식회사 TBGA semiconductor package and the fabrication method of the same

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