KR100833941B1 - TBGA semiconductor package - Google Patents

Abstract

A TV package is disclosed. The present invention is a circuit tape having a film having a predetermined cavity, a circuit pattern layer patterned on the film, and a photosolder register formed on a portion of the circuit pattern layer; and on the opposite side of the film on which the circuit pattern layer is formed. A frame formed by electroplating through a conductive layer material, and a semiconductor chip mounted on a cavity formed in the film and electrically connected to the circuit pattern layer.

Description

TVA semiconductor package {TBGA semiconductor package}

1 is a cross-sectional view schematically showing a conventional TVA semiconductor package;

2 is a cross-sectional view schematically showing a state in which a circuit tape is attached to the frame of FIG. 1;

3 is a flowchart illustrating a process of combining the frame and the circuit tape of FIG.

4 is a cross-sectional view schematically showing a TVA semiconductor package according to an embodiment of the present invention;

5A to 5F illustrate a state after the frame and the circuit tape of FIG. 4 are manufactured step by step.

5A is a cross-sectional view showing a state after a metal thin film is formed on a film;

5B is a cross-sectional view illustrating a state after the photoresist is applied to the film of FIG. 5A by exposure and development;

5C is a cross-sectional view illustrating a state after etching and peeling the film of FIG. 5B;

Figure 5d is a cross-sectional view showing a state after applying the photosolder register to the film of Figure 5c,

5E is a cross-sectional view showing a state after applying a protective film layer to the film of FIG. 5D and forming a frame;

5F is a cross-sectional view illustrating a state after removing the protective film layer of FIG. 5E;

FIG. 6 is a flowchart illustrating a process of combining the circuit tape and the frame of FIG.

<Brief description of the main parts of the drawing>

10,40 ... semiconductor package 11,41,51 ... circuit tape

12 ... adhesive 13,43,57 ... frame

14,44 ... semiconductor chip 16,46 ... molding material

Solderball 41a Film

41b, 54 Circuit pattern layer 41c, 55 Photosolder register

56.Protective layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TVA semiconductor package, and more particularly, to a method of combining a circuit tape and a frame attached thereto and a TVV semiconductor package having improved structure.

In general, a tape ball grid array (TBGA) semiconductor package is a one-piece type in which a circuit tape on which a circuit pattern layer is formed is directly attached onto a heat sink for dissipating heat. It can be classified into a two-piece type that is attached to a plurality of frames of stiffeners and heat sinks.

In the TVA semiconductor package, a semiconductor chip is mounted through a cavity formed in a frame, a semiconductor chip and a circuit pattern layer of a circuit tape are electrically connected by wires, and solder balls are formed on the solder ball land portion formed in the circuit pattern layer. This is the structure to be attached.

1 illustrates a conventional one-piece TVA semiconductor package 10.

Referring to the drawings, the semiconductor package 10 includes a circuit tape 11 having a circuit pattern layer formed thereon, a frame 13 attached to a lower surface of the circuit tape 11 via an adhesive member 12, and The semiconductor chip 14 mounted in the cavity 13a formed in the frame 13, the wire 15 for wire bonding the circuit tape 11 and the semiconductor chip 14, and a portion for molding the wire bonded portion are molded. A molding material 16 and a solder ball 17 attached to the circuit tape 11 is included.

The semiconductor package 10 prepares and laminates the circuit tape 11 and the frame 13 to attach the circuit tape 11 to the frame 13.

FIG. 2 illustrates a state in which the circuit tape 11 and the frame 13 are attached to each other, and FIG. 3 illustrates a flow chart showing the coupling process step by step.

Here, the same reference numerals as in the above-described drawings indicate the same members having the same function.

Referring to Figures 2 and 3, the manufacturing process of the conventional circuit tape 11 and the frame 13 as follows.

First, a polymer film 11a such as polyimide is prepared, and a metal foil is attached onto the film 11a via a first adhesive member 21. (S10) Next, the metal foil is coated with a conventional photo. The circuit pattern layer 11b is formed by patterning through a lithography process. On the film 11a on which the circuit pattern layer 11b is formed, a photo solder resistor (PSR) 11c is formed on a portion other than the circuit pattern layer 11b. (S20) Accordingly, the circuit pattern The circuit tape 11 on which the layer 11b is formed is completed. Subsequently, the second adhesive member 12 is attached to one surface of the film 11a, that is, the opposite surface on which the circuit pattern layer 11b is formed.

On the other hand, the frame 13 is coupled to the circuit tape 11, for example, a heat sink or a stiffener is provided. The frame 13 is provided in a strip state in which a plurality of guide holes, etc. for position alignment when attached to the circuit tape 11 are provided, and a cavity corresponding to a portion where the semiconductor chip is to be mounted is formed by half etching, etc., on the upper portion thereof. (S40)

Each of the circuit tapes 11 and the frame 13 thus provided tapes the circuit tape 11 to the frame 13, rolls by applying a predetermined pressure, and presses the laminate to laminate each other (S50). )

Subsequently, as is widely known, a semiconductor chip is mounted in a cavity, wire bonded, molded, and solder balls are attached to complete a TV package.

However, the manufacturing process of the conventional TVA semiconductor package has the following problems.

As described above, the process can be broadly classified into a process of manufacturing a circuit tape, a process of manufacturing a frame, a process of attaching an adhesive member to the circuit tape, and a process of attaching a circuit tape to the frame. The manufacturing process is complicated because the photolithography process, the taping process, the rolling process, and the pressing process further include detailed processes.

In addition, since the adhesive member 12 is interposed between the circuit tape 11 and the frame 13, a path for dissipating heat generated during driving of the semiconductor package is lengthened, thereby reducing heat dissipation efficiency.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide a TVA semiconductor package in which a manufacturing process is simplified and heat dissipation efficiency is improved by forming a frame coupled to one surface of a circuit tape by electroplating.

In order to achieve the above object, the TV package semiconductor package according to an aspect of the present invention,

A circuit tape having a film having a predetermined cavity, a circuit pattern layer patterned on the film, and an optical solder register formed on a portion of the circuit pattern layer;

A frame formed by electroplating on the opposite surface of the film on which the circuit pattern layer is formed via a conductive layer material; And                     

And a semiconductor chip mounted on the cavity formed in the film and electrically connected to the circuit pattern layer.

In addition, the conductive layer material is any one selected from a metal material or a conductive polymer material formed on one surface of the film.

Further, the frame is characterized in that it has a thickness of 0.02 to 0.7 millimeters.

Hereinafter, a TVA semiconductor package and a method of manufacturing the same according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 illustrates a TVA semiconductor package 40 according to an embodiment of the present invention.

Referring to the drawings, the semiconductor package 40 is mounted on a circuit tape 41, a frame 43 formed on the bottom surface of the circuit tape 41, and a cavity 43a formed on the frame 43. And a semiconductor chip 44.

The circuit tape 41 is formed on a polymer film 41a such as polyimide, a circuit pattern layer 41b patterned on the film 41a, and a portion where the circuit pattern layer 41b is not formed. And a photosolder register 41c.

The semiconductor chip 44 is wire bonded by the circuit pattern layer 41b and the first wire 45a. The semiconductor chip 44 including the wire bonded portion is molded with the molding material 46. In addition, a ground pad 48 is formed in the frame 43, and the semiconductor chip 44 is connected by the second wire 45b.                     

On the other hand, a solder ball 47 is attached on the circuit pattern layer 41b to be electrically connected to an external circuit board.

According to a feature of the invention, the frame 43 is formed on one surface of the circuit tape 41 by the electroplating method.

In more detail as follows.

5A through 5F illustrate a step of manufacturing a circuit tape and a frame step by step, and FIG. 6 is a flowchart sequentially illustrating the process.

First, a film 51 made of a polymer resin such as polyimide is provided. The first conductive layer 52a and the second conductive layer 52b made of a metal thin film, for example, copper are formed on both surfaces of the film 51. The first and second conductive layers 52a and 52b may be formed on the film 51 by sputtering or casting. In addition, one surface of the film 51 may be coated with a conductive polymer material instead of the conductive layer. (FIGS. 5A and T10).

Subsequently, the first conductive layer 52a forms a circuit pattern layer through a photolithography process (T20), that is, a photoresist 53 is coated on the first conductive layer 52a, and the exposure and It develops and forms a pattern (FIG. 5B).

Next, an etching process is performed using a predetermined etching solution to form the circuit pattern layer 54 on the upper surface of the film 51, and then peel off the remaining photoresist 53. As a result, a circuit pattern layer 54 formed under a predetermined design rule is completed on the upper surface of the film 51. (FIG. 5C).                     

After the circuit pattern layer 54 is completed, the photosolder register 55 is formed in a region where the circuit pattern layer 54 is not formed on the film 51. That is, the photosolder resistor raw material is printed on the film 51, exposed, developed, and dried to form the photosolder register 55 in a portion other than the circuit pattern layer 54 (FIG. 5D).

Subsequently, the protective film layer 56 is formed on the portion where the circuit pattern layer 54 is formed. The passivation layer 56 is formed to protect the upper portion of the film 51 including the circuit pattern layer 54 during a later plating process. The protective layer 56 is preferably a polymer resin such as PET, which may be formed in a film or paste form. (T30)

After the protective film layer 56 is formed, an electroplating method is performed by immersing the circuit tape, that is, the film 51 on which the circuit pattern layer 54 is formed, in an electrolytic bath. The second conductive layer 52b is formed on one surface of the film 51 and the opposite surface on which the circuit pattern layer 54 is formed. As a result, when the second conductive layer 52b is used as the cathode and the appropriate metal is used as the anode in the electrolyte in the electrolytic bath, an electrochemical reaction occurs. The plating layer having a predetermined thickness is formed on the second conductive layer 52b by reduction. Is formed.

In this embodiment, a copper plating layer is formed on the lower surface of the second conductive layer 52b. When such a plating layer is formed to have a suitable thickness, such as about 0.02 to 0.7 millimeter, the frame 57 is completed. Preferably, forming the frame 57 so that the thickness of the frame 57 is 0.5 millimeter may be advantageous to heat dissipation or to prevent deformation of the semiconductor package.                     

In other words, the metal foil provided separately is not attached to the bottom surface of the film 51, but the frame 57 is formed on the bottom surface of the film 51 on which the conductive layer 52b is formed by electroplating. In this case, the second conductive layer 52b may be selected from conductive metal materials or polymer materials. In addition, the frame 57 is preferably electroplated to have a thickness that is greater than or equal to that of the semiconductor chip in an assembly process (FIGS. 5E and T40).

After the frame 57 is completed, the protective film layer 56 formed to prevent plating on the circuit pattern layer 54 on the upper portion of the film 51 is peeled off to form the frame 57 under the circuit tape. ) Is completed. (FIG. 5F, T50).

Here, the formation of the cavity in which the chip is mounted is performed by etching the film 51 with respect to the cavity area after the circuit pattern layer 54 is formed on the film 51, thereby forming the upper circuit pattern layer 54 and the lower part. The second conductive layer 52b of is left. Thereafter, the process may be performed to form the frame 57 on the second conductive layer 52b so that the semiconductor chip may be formed into the cavity.

In this way, the semiconductor chip is mounted in the cavity formed in the film 51, the circuit pattern layer 54 and the semiconductor chip are wire-bonded, the semiconductor chip including the wire-bonded part is molded with a molding material, and the circuit pattern layer ( A solder ball is attached to the solder ball land formed in 54 to complete the TV package.

As described above, the TVA semiconductor package of the present invention and a method of manufacturing the same can obtain the following effects.

First, by forming a frame in the lower portion of the film by the electroplating method, the distance between the circuit pattern layer and the frame is shortened to improve heat dissipation efficiency.

Second, the process of manufacturing the circuit tape, the process of manufacturing the frame, and the process of combining them into one can be centralized, thereby simplifying the manufacturing process and significantly reducing errors that may occur during the manufacturing process.

Third, it can be seen that it is advantageous in terms of manufacturing cost by forming the frame by plating rather than foil of a thin film.

Fourth, according to the design of the semiconductor package, the circuit pattern layer and the frame can be directly connected, thereby improving electrical and thermal performance.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various changes and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (3)

A circuit tape having a film having a predetermined cavity, a circuit pattern layer patterned on the film, and an optical solder register formed on a portion of the circuit pattern layer; A frame formed by electroplating on the opposite surface of the film on which the circuit pattern layer is formed via a conductive layer material; And And a semiconductor chip mounted in a cavity formed in the film and electrically connected to the circuit pattern layer. The method of claim 1, The conductive layer material is TVS semiconductor package, characterized in that any one selected from a metal material or conductive polymer material formed on one surface of the film. The method of claim 1, And the frame has a thickness of 0.02 to 0.7 millimeters.

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