JP5092424B2 - Lead frame and manufacturing method thereof - Google Patents

Description

  The present invention relates to a lead frame for a surface-mount type resin-encapsulated semiconductor device and a manufacturing method thereof. The present invention also relates to a semiconductor package, a printed wiring board, and an electronic device using the lead frame.

  2. Description of the Related Art In recent years, semiconductor devices have been highly integrated and enhanced in performance, and a semiconductor package in which a semiconductor element (chip) is mounted on a lead frame is required to be reduced in size and thickness. In addition, the number of external terminals tends to increase with the high integration of chips, and various methods for mounting such chips have been developed and put into practical use.

As a chip mounted using a lead frame, a surface mount package called QFP (Quad Flat Package) is used and put into practical use. QFP uses a single-layer lead frame, and an inner lead electrically connected to a semiconductor element and an outer lead serving as a terminal for external connection are disposed on one surface of the lead frame. The QFP is produced by mounting a semiconductor element on a die pad, connecting the tip of the inner lead and the terminal of the semiconductor element with a wire, sealing the whole with resin, and bending the outer lead into a gull wing shape. Such a QFP has a structure in which outer leads are arranged so as to be electrically connected to an external circuit in four directions around the package, and has been developed so as to cope with the increase in the number of pins (terminals).

  QFP can cope with further increase in pin count by narrowing the external terminal pitch, but if the external terminal pitch is narrowed, it is necessary to narrow the width of the external terminal itself, which may reduce the strength of the external terminal. . Further, since the pitch of the external terminals is narrowed, there is a problem that it is difficult to mount these narrow pitch terminals.

  In order to solve the problems related to the mounting efficiency and mountability of these QFPs, a semiconductor package called BGA (Ball Grid Array), which is a surface mount package using solder balls as external terminals of the package, has been developed. BGA is a general term for semiconductor packages in which solder balls serving as external terminal electrodes are arranged in a matrix on one surface. Usually, in order to increase the number of terminals, a BGA has a semiconductor element mounted on one side and an external terminal with a spherical solder attached on the other side, and the semiconductor element and the external terminal are electrically connected through a through hole. Connecting. In BGA, the pitch of the terminal pitch can be made wider than the conventional QFP using a single-layer lead frame by arranging spherical solders in a matrix pattern. As a result, mounting of the semiconductor element is facilitated. It is possible to cope with an increase in output terminals.

  However, in the BGA, a semiconductor element mounted on a package and a circuit for connecting wires are provided on one surface, and external terminals for mounting the package after mounting the semiconductor device on a printed wiring board are provided on the other surface. . The circuit provided on one surface and the external terminal provided on the other surface need to be electrically connected through a through hole penetrating the substrate, and the manufacturing process of the BGA is complicated. Furthermore, the thermal expansion of the resin substrate may cause disconnection of the through-hole portion and reduce reliability.

  For this reason, in order to simplify the manufacturing process and avoid the problem of reliability, a BGA in which a circuit is formed using a lead frame as a core material has been proposed. Japanese Patent Application Laid-Open No. 8-139259 (Patent Document 1) discloses a lead frame formed by processing a metal plate, having an insulating layer, and having external terminals arranged in a grid pattern. The insulating layer of the lead frame of Patent Document 1 is disposed on the surface (opposite surface) opposite to the semiconductor element mounting side (chip mounting surface) of the lead frame and covers the entire resin-encapsulated region, but the external terminals are outside. The insulating layer is not covered so as to be exposed.

  Japanese Patent Application Laid-Open No. 9-307043 (Patent Document 2) includes at least an inner lead and an external terminal integrally connected to the inner lead, and a part thereof is thinner than the original thickness of the base material. A lead frame member for a resin-encapsulated semiconductor device is disclosed, which includes a lead frame formed on the substrate and an insulating resin that fixes the entire lead frame. The external terminals are two-dimensionally arranged along one surface (opposite surface) of the plate-like substrate, and are electrically connected to an external circuit. The lead frame member manufacturing method includes: (a) a step of forming a resist pattern having a predetermined pattern on both front and back surfaces after applying a photosensitive resist on both sides of a metal plate or the like as a base material; and (b) Performing at least a first etching process that forms a hole by etching from one surface of a base material on which a resist pattern is formed, and stopping the etching without penetrating the base material; and (c) a first etching process. A step of embedding a curable insulating resin having etching resistance in a hole portion on one surface of the base material formed by the step (d), and (d) a second etching process for etching and penetrating from the other surface of the base material. And (e) polishing from one surface side of the lead frame to expose an external terminal portion formed by etching on at least one surface side. It is. The invention described in Patent Document 2 allows the inner lead and the external terminal to be fixed and the inner lead to be miniaturized by adopting the above-described structure and manufacturing method.

JP-A-8-139259 Japanese Patent Laid-Open No. 9-307043

  However, the insulating layer of Patent Document 1 is a photosensitive film or a film with an adhesive. The former is formed by forming a lead frame by metallizing the base material, then sticking a photosensitive resin to the lead frame, and exposing and developing a film-like tourism resin. In the latter, holes for exposing the external terminals are formed in advance in the film, and alignment is performed so that the external terminals are exposed from the holes, and the film is laminated on the lead frame. For this reason, after forming the lead frame, it is necessary to attach a photosensitive resin, expose and develop the number of manufacturing steps, and it is also necessary to align and expose the lead frame already formed. On the other hand, in the latter case, it is necessary to laminate the film while aligning the film so that the external terminals are exposed from the holes formed in the film with adhesive. There is a problem.

  Moreover, in the lead frame of Patent Document 1, since the lead frame is formed by etching or pressing both sides of the base material, the inner leads, leads, and external terminals all have the same thickness. Therefore, when narrowing the pitch, it is necessary to reduce the thickness of the base material, which makes it more difficult to form and bond the insulating layer.

  In the manufacturing method of Patent Document 2, a step of polishing the embedded cured resin so as to be thin and accurately expose the external terminal portion is necessary. The thickness of the embedded cured resin is about half the thickness of the lead frame material and is weak in strength, and cracks may occur in the resin during the polishing process. In addition, when the external terminal is exposed, there is a possibility that a defect such that the external terminal part peels off and is pushed into the inner lead side may occur.

  The present invention has been made in view of the above-described circumstances, and is a BGA type resin-encapsulated semiconductor device and a lead frame used therefor, which can cope with a large number of pins and a narrow pitch, and is a simple method. It is an object of the present invention to provide a lead frame that can be manufactured and a manufacturing method thereof.

  The inventors of the present invention have made extensive studies to solve the above problems, and by half-etching a part of the surface to be the chip mounting surface of the base material, specifically, a portion excluding the region where the lead is formed, The inventors have found that the above problems can be solved and have completed the present invention. Specifically, the present invention provides the following.

The invention according to claim 1 is a lead frame comprising at least a lead and an external terminal electrically connected to the lead, and having a chip mounting surface and an opposite surface on the side opposite to the chip mounting surface. A part of the mounting surface is half-etched so that the distance to the connection surface of the external terminal on the opposite surface is shorter than the other part, and the lead is located in the other part on the chip mounting surface, and the lead Is etched from the opposite surface side, and is recessed on the chip mounting surface side compared to the connection surface of the external terminal on the opposite surface, and the chip connection terminal electrically connected to the external terminal via the lead The chip connection terminals are arranged in a matrix on the opposite surface, away from one side corresponding to a frame portion to which the external terminals are coupled, A lead frame, characterized in that disposed on the other edge near the position of the three sides except one side of the frame portion.

  The lead frame according to the present invention is produced by etching a base material from both sides, and one side of the base material, which is a chip mounting surface side, is half-etched except for a portion to be a lead. Thinner than the wood. In this way, by thinning the portion other than the portion that becomes the lead, according to the present invention, it is possible to achieve high definition of the etching of the lead, and lead with a wiring rule having a narrower pitch than that which is not thinned. Can be formed.

  On this lead frame, an insulating layer can be collectively formed only in a necessary portion by a resin molding process. For this reason, it is not necessary to form an insulating layer so as to expose the external terminal as in Patent Document 1, and a process of polishing a portion buried with a cured resin so as to expose the external terminal as in Patent Document 2 is necessary. Absent.

  In the lead frame according to the present invention, the portion where the lead is formed is half-etched from the side opposite to the chip mounting surface by performing the second etching, and is thinner than the base material. For this reason, high definition can be achieved as compared with the case where the lead is formed in the same thickness as the original base material. Moreover, since the lead does not appear on the same plane as the connection surface of the external connection terminal, only the external terminal portion can be exposed by peeling the fixing tape from the opposite surface after resin molding.

  The lead frame according to the present invention is a BGA type in which a plurality of external terminals are arranged in a matrix on the opposite side of the substrate, and the pitch of the external terminals is narrowed like the QFP type in which a plurality of external terminals are arranged in one direction. It is possible to cope with the increase in the number of pins without having to do so.

  The chip connection terminal is on the chip mounting surface opposite to the connection surface of the external terminal, and is electrically connected to the IC chip mounted on the chip mounting surface side. In the lead frame according to the present invention, it is possible to reduce the necessity of narrowing the pitch between the chip connection terminals by disposing the chip connection terminals on the outer peripheral side from the external terminals.

  If the portion of the substrate where the chip connection terminals are formed is thinned, it may become hollow and it may be difficult to maintain the shape. The chip connection terminal is wire-bonded to the chip during the chip mounting process. However, if the chip connection terminal is hollow, wire bonding becomes difficult. In the lead frame according to the present invention, the chip connection terminal is not thinned, and the same thickness as that of the base material is maintained, thereby facilitating wire bonding.

  In the lead frame of the present invention, since the tape is attached to the opposite surface where the connection surface of the external terminal is present, it is possible to prevent deformation of the lead frame having a portion through which the base material is penetrated. Since the tape can be peeled after the chip is mounted and resin molded, it is easy to obtain a semiconductor device having a structure in which the external terminals are exposed by peeling the tape after resin molding.

  A semiconductor package according to claim 7 is obtained by mounting a chip on the chip mounting surface side of the lead frame described above and processing the chip by resin molding. The semiconductor package can be mounted on a printed wiring board and mounted on an electronic device. Examples of the electronic device include a highly integrated device on which a small and thin semiconductor package is mounted, such as a notebook personal computer, a mobile phone, a PDA (personal digital assistant, personal digital assistance), and a game machine.

(A ) a step of applying a photoresist on both surfaces of a plate-like substrate and exposing to form a desired resist pattern; and (b) one surface of the substrate on which the resist pattern is formed as a chip mounting surface. The other surface opposite to the chip mounting surface is set as the opposite surface, and the first surface is formed by etching the chip mounting surface while protecting the opposite surface with a protective sheet so as to prevent the opposite surface from touching the etching solution. Performing a first etching; (c) applying a resin having etching resistance so as to cover the first hole and the chip mounting surface; and (d) applying the protective sheet from the opposite surface. Peeling and etching the opposite surface to form a second hole, and (e) heat resistance that can withstand an IC chip mounting process on the opposite surface that has been subjected to the second etching. Sex tape A method of manufacturing a lead frame comprising at least a bonding step and (f) a step of peeling off the resin having etching resistance.

  According to the present invention, it is not necessary to form an insulating layer so as to expose the external terminal, and only the external terminal is exposed without polishing the portion buried with the cured resin so as to expose the external terminal. Can be manufactured easily.

  According to the present invention, it is possible to provide a lead frame that can cope with an increase in the number of terminals and a high definition, can be manufactured by a simple method with a small number of processes, and a manufacturing method thereof.

  Hereinafter, the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same member and description is abbreviate | omitted or simplified. In the drawings, each member is appropriately reduced or enlarged for convenience of explanation.

  FIG. 1A is a schematic plan view of a lead frame 100 according to the first embodiment of the present invention, FIG. 1B is a cross-sectional view taken along line XX of FIG. ) Is a cross-sectional view taken along line YY of the portion surrounded by the broken line in FIG. In these figures, for convenience of explanation, some of the terminals are omitted, and the number of terminals actually provided is larger than shown in the figures.

  The lead frame is obtained by etching using a metal substrate as a base material, and has a thin plate shape as a whole. The material of the substrate is not particularly limited, and is made of, for example, Fe-42Ni or a copper alloy.

  One side of the lead frame is the chip mounting surface on which the chip is mounted, and when mounted on a printed wiring board, etc., the chip mounting surface is the upper side and the opposite side (hereinafter referred to as the “opposite surface”) Mounted on the wiring board as the lower side. The lead frame 100 according to the first embodiment includes an external terminal 101, a chip connection terminal 102, a lead 103, a die pad 104, a frame portion 105, and a tape 106.

  The frame portion 105 defines the outer edge of the lead frame 100, and the shape thereof is not limited. However, in the present embodiment, the frame portion 105 is substantially rectangular. As described above, the lead frame 100 according to the first embodiment has a substantially rectangular thin plate shape in plan view as a whole, and as shown in FIG. 1B, the chip mounting surface S and the opposite surface R are in the thickness direction of the plate. The tape 106 is stuck on the opposite surface R.

  The external terminal 101, the chip connection terminal 102, the lead 103, and the die pad 104 are disposed inside the frame portion 105. The die pad 104 is disposed substantially at the center of the frame portion 105, and the lead 103 is located between the external terminal 101 and the chip connection terminal 102 to connect them.

  A connecting portion 107 extends from the external terminal 101 to the opposite side of the lead 103, and one end (hereinafter referred to as “base end”) of the connecting portion 107 is connected to the frame portion 105. That is, the external terminal 101, the lead 103, and the chip connection terminal 102 are arranged in this order away from the frame portion 105 and toward the center.

  As shown in FIG. 1A, the inside of the frame portion 105 is hollow except for the portions where the external terminals 101, the chip connection terminals 102, the leads 103, the die pad 104, the frame portion 105, and the connecting portion 107 exist. Yes. As shown in FIG. 1B, in the lead frame 100, on the chip mounting surface S side, the external terminals 101, the leads 103, the frame portion 105, and the connecting portion 107 are substantially in the same plane (the first plane). The chip connection terminal 102 and the die pad 104 are on another substantially identical plane (second plane) on the opposite surface R side from the first plane. In FIG. 1C, the first plane is indicated by a one-dot broken line denoted by reference numeral S1, and the second plane is indicated by a two-dot broken line denoted by reference numeral S2.

  As described above, the chip mounting surface S including one side of the external terminal 101, the chip connection terminal 102, the lead 103, the die pad 104, the frame portion 105, and the connecting portion 107 has irregularities, and the chip mounting surface S A portion where the chip connection terminal 102 and the die pad 104 are present (hereinafter sometimes referred to as a “thin portion”) is recessed toward the opposite surface R as compared with the other portions.

  On the other hand, on the opposite surface R side, the external terminal 101, the chip connection terminal 102, the lead 103, the die pad 104, the frame portion 105, and the connecting portion 107 all appear on the same plane except for the lead 103 and the connecting portion 107. The surface on the opposite surface R side of the external terminal 101 is a connection surface to which an external circuit is connected, and the surface height of the external terminal 101 is the reference height of the opposite surface R. As described above, since the chip mounting surface S has irregularities, when the opposite surface R side surface (connection surface) of the external terminal 101 is the reference height of the opposite surface R, the thin portion of the chip mounting surface S Compared to the portion, the distance to the reference height of the opposite surface R is short. This is because, in the manufacturing process of the lead frame 100, when the chip mounting surface S side is etched, at least a portion excluding the lead 103 is half-etched and thinned.

  Hereinafter, a method of manufacturing the lead frame 100 will be described with reference to FIG.

  First, the metal substrate 31 is prepared as a base material. The type of metal is, for example, Fe-42Ni or a copper alloy, and the thickness of the substrate 31 is 0.05 mm or more and 0.2 mm or less, preferably 0.1 mm or more and 0.15 mm or less.

  After degreasing and cleaning the substrate 31, a photoresist 32 is applied to both surfaces of the substrate 31 (see FIG. 2A). The layer of the photoresist 32 may be either a negative type or a positive type, and examples of the negative type photoresist include bichromic acid type, polycinnamate vinyl type, and cyclized rubber azide type. Examples of the positive photoresist include naphthoquinone azide and novolak resin.

  The method for forming the photoresist layer is not particularly limited, but when a liquid photoresist is applied, a commonly used photoresist coating method using a spin coater, a roll coater, a dip coater or the like is used. When a dry film resist is used, a laminator is used. Alternatively, a photoresist layer may be formed by pattern printing of a printing resist.

  Next, exposure is performed by aligning the front and back surfaces through a photomask 33 on which a pattern consisting of light-transmitting or light-shielding portions is formed (see FIG. 2B). Thereafter, development is performed to form a photoresist pattern having a desired pattern (see FIG. 2C). In this embodiment, the photoresist pattern 34S formed on the chip mounting surface 31S side is a pattern of the leads 103, the external terminals 101, the connecting portions 107, and the frame portions 105. On the other hand, the photoresist pattern 34 </ b> R formed on the opposite surface 31 </ b> R side has the shape of the external terminal 101, the chip connection terminal 102, the die pad 104, and the frame portion 105.

  Next, 1st etching is performed with respect to the single side surface 31S used as the chip | tip mounting surface of the base material 31. FIG. When performing the first etching, as shown in FIG. 2D, the protective sheet 35 may be attached to the opposite surface 31R so that the opposite surface 31R of the base material 31 does not touch the etching solution. For the etching, an etching solution capable of corroding a metal plate such as ferric chloride solution or cupric chloride solution is used, and the first etching (half etching) is performed by using a spray method or the like, and the chip mounting surface 31S. A first hole 36 is formed in (see FIG. 2E).

  Since the photoresist pattern 34S on the chip mounting surface 31S side has a pattern shape of the lead 103, the external terminal 101, the connecting portion 107, and the frame portion 105, the first hole portion 36 corresponds to other portions. To do. As described above, in this embodiment, a part of the chip mounting surface 31S (except for the part that becomes the lead 103, the external terminal 101, the connecting part 107, and the frame part 105) is etched, and the other part (that is, the lead 103, the external terminal 101, The connecting portion 107 and the portion that becomes the frame portion 105) are not etched. For this reason, a part of the chip mounting surface 31 </ b> S (except for the part that becomes the lead 103, the external terminal 101, the connecting part 107, and the frame part 105) is substantially at the same height as the original surface of the base material 31. Compared to the portion (the portion that becomes the lead 103, the external terminal 101, the connecting portion 107, and the frame portion 105), it is recessed toward the opposite surface 31R.

  After forming the first hole 36 in the chip mounting surface 31S, the photoresist pattern 34S applied to the chip mounting surface 31S and used for the first etching is peeled off with an alkaline aqueous solution such as sodium hydroxide. Next, a hardened resin 37 having etching resistance is applied to the chip mounting surface 31S of the base material 31 including the first hole portion 36 formed by the first etching to fill the first hole portion 36 ( (Refer FIG.2 (f)). As the cured resin having etching resistance, hot melt wax, UV cured varnish, or the like can be used, and a resin that can be peeled off by hot alkali or the like later is used. Roll coating, curtain coating, dip coating, bar coating, and the like can be used as a method for applying the cured resin.

  Next, the protective sheet 35 attached to the opposite surface 31S is peeled off, and the second etching is performed on the opposite surface 31S in the same manner as in the first etching method to form the second hole 38 in the opposite surface 31S. (See FIG. 2 (g)). Since the photoresist pattern 34R on the opposite surface 31 side, the external terminal 101, the chip connection terminal 102, the die pad 104, and the frame portion 105 are formed in shape, the second hole portion 38 corresponds to other portions.

  Here, in the present embodiment, a part of the chip mounting surface 31S (other than the part that becomes the lead 103, the external terminal 101, the connecting part 107, and the frame part 105) is etched by the first etching, and the other part (the lead 103). The outer terminal 101, the connecting portion 107, and the frame portion 105) are thinner. For this reason, when the opposite surface 31S side is etched by the second etching, the part that is thinner than the other part except the photoresist pattern 34R on the opposite surface 31S side is first of the base 31 It penetrates the front and back. As described above, when the second etching depth is a depth at which only a part of the chip mounting surface 31S thinned by the first etching penetrates the base material 31, the first etching and the second etching are performed. Only the portions other than the remaining portions (the leads 103, the external terminals 101, the chip connection terminals 102, the coupling portions 107, and the frame portions 105) are hollow portions that are penetrated through the base material 31 and are removed.

  As described above, when a part of the chip mounting surface 31S, in particular, the portion where the lead 103 and the external terminal 101 are formed is half-etched and thinned by the first etching, a high-definition wiring is easily formed. Hereinafter, this point will be described with reference to FIGS.

  FIG. 4A shows a case where a lead frame is formed by a conventional method in which the chip mounting surface 31S is not half-etched, and is a schematic cross-sectional view of a portion corresponding to the portion shown in FIG.

  When the metal substrate 31 is wet etched, since the wet etching is isotropic etching, the etching is performed not only in the vertical (thickness) direction of the base material 31 but also in the horizontal direction (direction in which the surface spreads) perpendicular thereto. Also proceeds and side etching occurs. Therefore, if etching is performed to a certain depth or more with respect to the opening of the photoresist resist and the base material 31 is penetrated, side etching that proceeds in the horizontal direction occurs. The leads 103 cannot be arranged at a narrow pitch. On the other hand, if the etching depth is reduced in order to avoid side etching, conventionally, as shown in FIG. For this reason, in order to penetrate L1 between the leads 103, penetration processing is required, but it is difficult to penetrate fine wiring.

  On the other hand, according to the present invention, half etching is performed in which the first etching etches a part of the chip mounting surface 31S, specifically, a part including a part that allows the base material 31 to penetrate. For this reason, in the second etching, even if the etching is finished at a depth that avoids the influence of side etching, it is possible to penetrate the portion where the base material 31 is to penetrate. Therefore, L1 between the leads 103 can be narrowed, and highly accurate wiring processing can be performed.

  The half etching in the first etching may be performed on at least a portion other than the portion where the lead 103 is formed. However, in the case where the portion where the external terminal 102 is formed is not half-etched as the other part of the chip mounting surface 31S, as shown in FIG. 4C, in order to penetrate L2 between the external terminal 102 and the lead 103. Deep etching or through processing is required, and L2 between the lead 103 and the external terminal 102 cannot be narrowed. For this reason, as in the present embodiment, in the first etching, not only the portion where the substrate 31 is desired to penetrate, but also the portion where the external terminal 102 is formed is half-etched as a part of the chip mounting surface 31S, It is preferable to perform etching so that the external terminal 102 is left by etching 2. Thus, according to the present invention, the space between the lead 103 and the external terminal 102 can be narrowed, and the degree of freedom in design and high definition can be achieved.

  After the second hole 38 is formed in the opposite surface 31R by the second etching, the photoresist pattern 34R applied to the opposite surface 31R and used for the second etching is peeled off. When the cured resin is thin or when the metal substrate has many through holes and it is difficult to maintain the shape, a protective sheet (not shown) may be laminated on the surface of the cured resin 37 and etched.

  Next, the tape 39 is affixed to the entire opposite surface 31R (see FIG. 2 (h)). As the tape 39, it is preferable to use a heat-resistant tape that can be peeled after an IC chip is mounted on the chip mounting surface 31S. Specific examples include those in which a thermoplastic adhesive is applied to a polyimide film.

  Here, the portion where the lead 103 and the connecting portion 107 are formed is the other portion that is not etched during the first etching, but is etched during the second etching. That is, the lead 103 and the connecting portion 107 are etched when the opposite surface 31R is etched by the second etching, and are recessed toward the chip mounting surface 31S side and thinner than the connection surface of the external terminal 102. For this reason, when the tape 39 is attached on the same plane as the connection surface of the external terminal 102, the tape 39 is not bonded to the lead 103 and the connecting portion 107. That is, the portion bonded to the tape 39 is only the external terminal 101, the chip connection terminal 102, and the frame portion 105 that are the portions left by the second etching. The connection surface can be exposed.

  Thereafter, the cured resin 37 is peeled off by hot alkali to obtain the lead frame 100 shown in FIG. 1 (see FIG. 2 (i)). The lead frame 100 is formed into a semiconductor package by mounting an IC chip (not shown) on a portion of the chip mounting surface where the die pad 104 is formed and sealing with resin. In the IC chip mounting process, die bonding, wire bonding, epoxy resin molding, and the like are performed, and the workpiece may be exposed to a temperature of about 190 ° C. for several hours. For this reason, the tape to be attached to the opposite surface of the lead frame 100 is a tape that can be peeled off from the sealing material and the lead frame after preventing leakage of the sealing material during sealing.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to this, It can change suitably in the range which does not deviate from the technical idea of the invention.

  FIG. 3A shows a schematic plan view of an IC chip 210 mounted on the lead frame 200 according to the second embodiment of the present invention, and FIG. 3B shows the IC chip 210 sealed with a resin 220. The cross-sectional schematic diagram of the semiconductor package 250 formed is shown. FIG. 3B is a schematic cross-sectional view taken along line XX in FIG. In these figures, for convenience of explanation, some of the terminals are omitted, and the number of terminals actually provided is larger than shown in the figures.

  Similar to the lead frame 100 according to the first embodiment, the lead frame 200 according to the second embodiment includes an external terminal 201, a chip connection terminal 202, a lead 203, a die pad 204, a frame portion 205, and a tape 206. An IC chip 210 is mounted on the chip mounting surface S side of the die pad 204, the chip connection terminal 202 and the IC chip 210 are connected by a bonding wire 230, and the whole is molded with a resin 220.

  Hereinafter, the lead frame of the present invention will be described more specifically with reference to examples. The outline of the process is the same as the procedure shown in FIG.

[Example 1]
A 0.12-mm thin metal plate made of Fe-42Ni was prepared as a base material, and degreased by being immersed in an alkaline degreasing solution composed of sodium hydroxide, potassium hydroxide, and a surfactant at 55 ° C. for 10 minutes. Thereafter, a casein resist using potassium dichromate as a photosensitizer was applied on both surfaces of the substrate to a thickness of 10 μm by dip coating to form a photoresist layer. The substrate coated with photoresist on both sides was dried in an oven at 70 ° C. for 20 minutes, and then exposed and developed on both sides with a photomask having a predetermined pattern to form an etching resistant resist pattern.

  The resist pattern on one surface of the substrate was a pattern of leads, external terminals, connecting portions, and a frame portion, and the other surface was a pattern of external terminals, chip connection terminals, die pads, and a frame portion. This one surface was used as a chip mounting surface to be etched by the first etching, and a protective sheet having etching resistance was laminated on the other surface (opposite surface) opposite to this surface. Subsequently, the chip mounting surface was subjected to first etching by spray etching with ferric chloride solution at 65 ° C. and 0.4 MPa to form a first hole that was depressed on the opposite surface side.

  Thereafter, the photoresist used in the first etching was peeled off, and an anti-etching varnish was applied so as to fill the depressed hole on the chip mounting surface where the photoresist was peeled off. As the etching preventing varnish, a hot melt resin, which is an ethylene-acrylic acid copolymer resin that softens up to 1000 cps at 170 ° C., was used. This resin is an alkali-dissolving wax, and is a cured resin having resistance to etching and having resistance to acidic etching solutions. The hot melt resin was applied to the chip mounting surface of the substrate so as to have a film thickness of 50 μm by a die coater method.

  Next, the protective sheet was peeled off from the surface opposite to the chip mounting surface etched by the first etching, and second etching was performed to etch the surface on the opposite side in the same manner as the first etching. After performing the second etching, the photoresist was peeled off from the second etched surface. Next, after heat-resistant tape (RT-321, manufactured by Hitachi Chemical Co., Ltd.) is laminated on the second etching surface from which the photoresist has been peeled off at a temperature of 260 ° C., an aqueous solution comprising potassium hydroxide and a surfactant is added at 50 ° C. Was immersed for 10 minutes, and the etching preventing varnish applied to the chip mounting surface side was peeled off.

  Of the chip mounting surface from which the etching preventing varnish was peeled off, the portion where the chip connection terminals were formed was subjected to silver plating so that wire bonding was possible, and the lead frame according to Example 1 of the present invention was obtained.

  An IC chip was mounted on a die pad on the chip mounting surface side of the lead frame and connected to a chip connection terminal by wire bonding. Next, after the chip mounting surface was mold-sealed with an epoxy resin, the heat-resistant tape was peeled off from the opposite surface, whereby a resin-sealed semiconductor device could be obtained.

[Example 2]
Next, Example 2 will be described. A thin metal plate made of Fe-42Ni having a thickness of 0.15 mm was prepared as a base material, and degreased by being immersed in an alkaline degreasing solution composed of sodium hydroxide, potassium hydroxide, and a surfactant at 55 ° C. for 10 minutes. Thereafter, a dry film resist (AQ2038, manufactured by Asahi Kasei Electronics Co., Ltd.) having a thickness of 20 μm was laminated on both surfaces of the base material to form a photoresist layer. The base material on which the photoresist layer was formed was subjected to double-sided exposure and development with a photomask having a predetermined pattern to obtain an etching-resistant resist pattern.

  The resist pattern is the same as in Example 1, and the surface on which the shape of the lead, external terminal, connecting portion, and frame portion is patterned is the mounting surface, and the opposite surface is the opposite surface, and the opposite surface has etching resistance. The protective sheet having the laminate was laminated. Next, the chip mounting surface was subjected to first etching by spray etching with ferric chloride solution at 50 ° C. and 0.3 MPa to form a first hole.

  After forming the first hole, the photoresist used in the second etching is peeled off, and UV curing varnish for etching prevention is applied by die coating so that the hole is filled in the surface, and then irradiated with ultraviolet light. Cured. The varnish used here is an alkali-dissolving wax, and is a cured resin that is resistant to an acidic etchant.

  Next, the protective sheet was peeled from the opposite surface, and a second etching was performed in which the opposite surface was etched in the same manner as the first etching. After the second etching, the photoresist on the opposite surface was stripped. Next, heat-resistant tape (RT-321 manufactured by Hitachi Chemical Co., Ltd.) is laminated on the opposite surface from which the photoresist has been peeled off at a temperature of 260 ° C., and immersed in an aqueous solution of potassium hydroxide and a surfactant for 10 minutes at 50 ° C. Then, the UV curing varnish for preventing etching was peeled off.

  Of the chip mounting surface from which the varnish was peeled, the portion where the chip connection terminal was formed was subjected to nickel plating and gold plating so that wire bonding was possible, and the lead frame according to Example 2 of the present invention was obtained.

  An IC chip was mounted on a die pad on the chip mounting surface side of the lead frame and connected by wire bonding. Thereafter, the whole was mold-sealed with an epoxy resin, and the heat-resistant tape on the opposite surface was peeled off to obtain a resin-sealed semiconductor device.

  The present invention can be applied to a semiconductor package mounted on a printed wiring board or the like.

The schematic diagram of the lead frame concerning a 1st embodiment of the present invention. The figure explaining the manufacturing process of the lead frame which concerns on 1st Embodiment. The schematic diagram of the lead frame concerning a 2nd embodiment of the present invention. The figure explaining the process of forming a lead and an external terminal.

Explanation of symbols

100, 200 Lead frame 101, 201 External terminal 102, 202 Chip connection terminal 103, 203 Lead 104, 204 Die pad 105, 205 Frame portion 106, 206 Tape 107, 207 Connection portion 210 Chip 220 Resin 250 Semiconductor package

Claims (2)

In a lead frame comprising at least a lead and an external terminal electrically connected to the lead, and having a chip mounting surface and an opposite surface opposite to the chip mounting surface,
A part of the chip mounting surface is half-etched and the distance to the connection surface of the external terminal on the opposite surface is shorter than the other part,
In the chip mounting surface, the lead is located in the other part, and the lead is etched from the opposite surface side, and the opposite surface is recessed toward the chip mounting surface side compared to the connection surface of the external terminal,
A chip connection terminal electrically connected to the external terminal via the lead; and the chip connection terminal is arranged in a matrix on the opposite surface, from one side corresponding to a frame portion to which the external terminal is connected A lead frame characterized in that the lead frame is disposed at a position close to the outer edge of the other three sides other than the one side of the frame portion. The lead frame manufacturing method according to claim 1,
(A) applying a photoresist on both sides of a plate-like substrate, exposing to form a desired resist pattern;
(B) One side of the base material on which the resist pattern including the pattern shape of the lead and the external terminal is formed is a chip mounting surface, and the other surface opposite to the chip mounting surface is an opposite surface. A step of performing a first etching to form a first hole by etching the chip mounting surface by protecting with a protective sheet so as to prevent the surface from touching the etchant;
(C) applying a resin having etching resistance so as to cover the first hole and the chip mounting surface;
(D) A second hole is formed by peeling the protective sheet from the opposite surface and etching the opposite surface on which the resist pattern including the pattern shape of the external terminal and the chip connection terminal is formed . 2 etching steps;
(E) attaching a heat-resistant tape that can withstand an IC chip mounting process to the second etched surface;
(F) A method for producing a lead frame, comprising: a step of peeling the resin having etching resistance.